32-bit Power Architecture MCU for Automotive Powertrain Applications

The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).

Key Features

  • 150 MHz e200z4 Power Architecture core
    • Variable length instruction encoding (VLE)
    • Superscalar architecture with 2 execution units
    • Up to 2 integer or floating point instructions per cycle
    • Up to 4 multiply and accumulate operations per cycle
  • Memory organization
    • 4 MB on-chip flash memory with ECC and Read While Write (RWW)
    • 192 KB on-chip RAM with standby functionality (32 KB) and ECC
    • 8 KB instruction cache (with line locking), configurable as 2- or 4-way
    • 14 + 3 KB eTPU code and data RAM
    • 5 × 4 crossbar switch (XBAR)
    • 24-entry MMU
    • External Bus Interface (EBI) with slave and master port
  • Fail Safe Protection
    • 16-entry Memory Protection Unit (MPU)
    • CRC unit with 3 sub-modules
    • Junction temperature sensor
  • Interrupts
    • Configurable interrupt controller (with NMI)
    • 64-channel DMA
  • Serial channels
    • 3 × eSCI
    • 3 × DSPI (2 of which support downstream Micro Second Channel [MSC])
    • 3 × FlexCAN with 64 messages each
    • 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
  • 1 × eMIOS
    • 24 unified channels
  • 1 × eTPU2 (second generation eTPU)
    • 32 standard channels
    • 1 × reaction module (6 channels with three outputs per channel)
  • 2 enhanced queued analog-to-digital converters (eQADCs)
    • Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers
    • 6 command queues
    • Trigger and DMA support
    • 688 ns minimum conversion time
  • On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
  • Nexus: Class 3+ for core; Class 1 for the eTPU
  • JTAG (5-pin)
  • Development Trigger Semaphore (DTS)
  • Clock generation
    • On-chip 4–40 MHz main oscillator
    • On-chip FMPLL (frequency-modulated phase-locked loop)
  • Up to 120 general purpose I/O lines
    • Individually programmable as input, output or special function
    • Programmable threshold (hysteresis)
  • Power reduction mode: slow, stop and stand-by modes
  • Flexible supply scheme
    • 5 V single supply with external ballast
    • Multiple external supply: 5 V, 3.3 V and 1.2 V
  • Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD)



Description Version Size
32-bit MCU family built on the embedded Power Architecture® 9.0 1 MB
Description Version Size
eTPU assembly converter 2.1 89 KB
Analyzing flash accesses with Lauterbach Trace32 5.0 556 KB
Developing self tests for SPC564Ax 2.1 180 KB
ECU level diagnostic with SPC563Mx and SPC564Ax 2.1 216 KB
Flash programming through Nexus/JTAG 3.0 999 KB
Hardware design guideline power supply and voltage measurement 3.0 1 MB
Hw recommendations for SPC564Axx / SPC563Mxx 2.1 657 KB
Porting eTPU code to eTPU compiler build tools guides 2.1 63 KB
RPC56xx and SPC56xx C90FL Flash recovery in case of brownout during Flash erase operation 2.0 165 KB
SPC564Axx/RPC564Axx/SPC56ELxx/RPC56ELxx devices Exception handling and single/double bit error 3.0 316 KB
Safety application guide forSPC564Axx/RPC564Axx family 3.0 365 KB
Shrinking the AUTOSAR OS: code size and performance optimizations 2.0 87 KB
Using the eTPU angle clock 2.1 269 KB
eTPU compiler tools 2.1 1 MB
eTPU host interface 2.0 292 KB
Description Version Size
Variable-Length Encoding (VLE) extension -programming interface manual 1.3 421 KB
uTester 1.0 2 MB
Description Version Size
Programmer's reference manual for Book E processors 2.0 24 MB
SPC564A74xx, SPC564A80xx 32-bit MCU family built on the embedded Power Architecture® 8.2 13 MB
SPC56xx and RPC56xx DSP function library 2 3.0 655 KB
Description Version Size
Signal processing engine (SPE) APU programming interface manual 3.2 1 MB
Description Version Size
SPC564A74x, SPC564A80x devices errata JTAG_ID = 0x2AE02041 1.0 228 KB
SPC564A74xx, SPC564A80xx device errata JTAG_ID = 0x1AE02041 6.0 105 KB


Description Version Size
SPC5 32-bit microcontroller Series featuring Power Architecture 2 MB
SPC5 Family Overview October 2015 2 MB


Description Version Size
All you need to drive SPC56 32-bit power architecture MCUs 1.0 1 MB
Driving Electromobility 1.0 1 MB


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型号 Marketing Status Packing Type CPU Clock Frequency (MHz) (max) FLASH Size (kB) (Data) Features set Operating Temperature (°C) (min) Operating Temperature (°C) (max) Unit Price (US$) * Quantity ECCN (EU) ECCN (US) Country of Origin More info Order from ST Order from Distributors
SPC564A74B4CFAY Active Tray 150 - Flexray -40 125 - - NEC 3A991A2 MALTA MORE INFO No availability reported, please contact our Sales office

(*) Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For quotes, prices in local currency, please contact your local ST Sales Office  or our Distributors


型号 Marketing Status Package Grade RoHS Compliance Grade Material Declaration**
SPC564A74B4CFAY ActivePBGA 324 23x23x1.82AutomotiveEcopack2 0 0

(**) The Material Declaration forms available on st.com may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.