STM32H7 series of high-performance MCUs with ARM® Cortex®-M7 core

Taking advantage of an L1 cache, STM32H7 devices deliver the maximum theoretical performance of the Cortex-M7 core, regardless if code is executed from embedded Flash or external memory: 2020 CoreMark /856 DMIPS at 400 MHz fCPU.

Smart architecture with new generation of peripherals set

The STM32H7 series unleashes the Cortex-M7 core:

  • AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
  • 16 Kbytes +16 Kbytes of I-cache and D-cache
  • Up to 2 Mbytes of embedded dual-bank Flash memory, with ECC and Read-While-Write capability
  • A high-speed master direct memory access (MDMA) controller, two dual-port DMAs with FIFO and request router capabilities for optimal peripheral management, and one additional DMA
  • Chrom-ART acceleration for efficient 2D image copy and double-precision FPU are also part of the acceleration features available in the device
  • Peripheral speed independent from CPU speed (dual-clock support) allowing system clock changes without any impact on peripheral operations
  • Even more peripherals, such as four serial audio interfaces (SAI) with SPDIF output support, three full-duplex I²S interfaces, a SPDIF input interface supporting four inputs, two USB OTG with dedicated power supply and Dual-mode Quad-SPI interface, two FD-CAN controllers, a high-resolution timer, a TFT-LCD controller, a JPEG codec, two SDIO interfaces and many other analog peripherals including three fast 16-bit ADCs, two comparators and two operational amplifiers.
  • 1 Mbyte of SRAM with a scattered architecture:
    • 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 512 Kbytes, 288 Kbytes and 64 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes

Security

Authenticate and protect your software IP while performing initial programming in production or firmware upgrades in the field (Available in 2018).

Power efficiency

  • The multi-power domains architecture allows the different power domains to be set in low-power mode to optimize the power efficiency. In addition to the main regulator featuring voltage scaling to supply the core in different voltage ranges during Run and Stop modes, the device also embeds a USB regulator to supply the embedded physical layer (PHY) and a backup regulator.
  • 263 µ/MHz typical @VDD = 3.3 V and 25 °C  in Run mode (peripherals off)
  • 4 µA in Standby mode (low-power mode)

Compatibility

  • Cortex-M7 is backwards compatible with the Cortex-M4 instruction set
  • STM32H7 series is pin-to-pin compatible with the STM32F7 series for common packages, and compatible with the STM32F4 series for most of the common packages *

* Note: see datasheet for the specific case of 100-pin packages

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