Component : VL53L9CX Registers Description

Description :

 

Block : REVISION_STATUS

Address

Name

Description

Reset

0x0000

DEVICE_MODEL_ID

DEVICE_MODEL_ID register

0x5333 4C39

0x0004

DEVICE_REVISION

DEVICE_REVISION register

0x0A00 A000

0x0008

UI_REVISION

UI_REVISION register

0x0204

0x000A

ROM_REVISION

ROM_REVISION register

0x0000

0x000C

PATCH_REVISION

PATCH_REVISION register

0x0000

0x0010

ROM_MD5_n[4]

ROM_MD5_n register

0x0000 0000

0x0020

RVST_RESERVED_n[2]

RVST_RESERVED_n register

0x0000 0000

2

 

Block : SENSOR_STATUS

Address

Name

Description

Reset

0x0028

FRAME_COUNTER

FRAME_COUNTER register

0x0000 0000

0x002C

TEMPERATURE

TEMPERATURE register

0x0000

0x002E

LDD_TEMPERATURE

LDD_TEMPERATURE register

0x0000

0x0030

LDD_POWER_CH0_n[7]

LDD_POWER_CH0_n register

0x0000

0x003E

LDD_POWER_CH1_n[7]

LDD_POWER_CH1_n register

0x0000

0x004C

REF_LONG_ST_CH1

REF_LONG_ST_CH1 register

0x0000 0000

0x0050

REF_LONG_ST_CH2

REF_LONG_ST_CH2 register

0x0000 0000

0x0054

REF_SHORT_ST_CH1

REF_SHORT_ST_CH1 register

0x0000 0000

0x0058

REF_SHORT_ST_CH2

REF_SHORT_ST_CH2 register

0x0000 0000

0x005C

CURRENT_FRAME_WIDTH

CURRENT_FRAME_WIDTH register

0x0000

0x005E

CURRENT_FRAME_HEIGHT

CURRENT_FRAME_HEIGHT register

0x0000

0x0060

CURRENT_STATIC_SETTINGS

CURRENT_STATIC_SETTINGS register

0x00

0x0061

AMBIENT_ATTENUATION

AMBIENT_ATTENUATION register

0x00

0x0062

CURRENT_DYNAMIC_SETTINGS

CURRENT_DYNAMIC_SETTINGS register

0x0000

0x0064

ERROR_CODE

ERROR_CODE register

0x0000

0x0066

ERROR_STATUS

ERROR_STATUS register

0x00

0x0067

LDD_ERROR_STATUS_n[5]

LDD_ERROR_STATUS_n register

0x00

0x006C

CURRENT_FRAME_PERIOD

CURRENT_FRAME_PERIOD register

0x0000 0000

0x0070

CROP_DSS_STATUS

CROP_DSS_STATUS register

0x0000 0000

0x0074

NB_SHOT_STEP_1_LSB

NB_SHOT_STEP_1_LSB register

0x00

0x0075

NB_SHOT_STEP_1_MID

NB_SHOT_STEP_1_MID register

0x00

0x0076

NB_SHOT_STEP_1_MSB

NB_SHOT_STEP_1_MSB register

0x00

0x0077

NB_SHOT_STEP_4_5_LSB

NB_SHOT_STEP_4_5_LSB register

0x00

0x0078

NB_SHOT_STEP_4_5_MID

NB_SHOT_STEP_4_5_MID register

0x00

0x0079

NB_SHOT_STEP_4_5_MSB

NB_SHOT_STEP_4_5_MSB register

0x00

0x007A

NB_SHOT_STEP_6_LSB

NB_SHOT_STEP_6_LSB register

0x00

0x007B

NB_SHOT_STEP_6_MID

NB_SHOT_STEP_6_MID register

0x00

0x007C

NB_SHOT_STEP_6_MSB

NB_SHOT_STEP_6_MSB register

0x00

0x007D

NB_SHOT_STEP_7_LSB

NB_SHOT_STEP_7_LSB register

0x00

0x007E

NB_SHOT_STEP_7_MID

NB_SHOT_STEP_7_MID register

0x00

0x007F

NB_SHOT_STEP_7_MSB

NB_SHOT_STEP_7_MSB register

0x00

0x0080

SEST_RESERVED_n[3]

SEST_RESERVED_n register

0x0000 0000

2

 

Block : FW_STATUS

Address

Name

Description

Reset

0x008C

SYSTEM_FSM

SYSTEM_FSM register

0x00

0x008D

COMMAND_ERROR

COMMAND_ERROR register

0x00

0x008E

FRAME_READY

FRAME_READY register

0x00

0x008F

XSTART

XSTART register

0x00

0x0090

YSTART

YSTART register

0x00

0x0091

FINAL_WIDTH

FINAL_WIDTH register

0x00

0x0092

FINAL_HEIGHT

FINAL_HEIGHT register

0x00

0x0094

FWST_RESERVED_n[10]

FWST_RESERVED_n register

0x0000 0000

2

 

Block : CONTROL

Address

Name

Description

Reset

0x0400

COMMAND

COMMAND register

0x00

0x0404

CTRL_RESERVED_n[10]

CTRL_RESERVED_n register

0x0000 0000

2

 

Block : BOOT_SETTINGS

Address

Name

Description

Reset

0x042C

EXT_CLOCK

EXT_CLOCK register

0x00B7 1B00

0x0430

INSTALL_PATCH

INSTALL_PATCH register

0x00

0x0431

SPI_FORMAT

SPI_FORMAT register

0x00

0x0434

LDD_OTP_CRC

LDD_OTP_CRC register

0x0000 0000

0x0438

VDDA_CFG

VDDA_CFG register

0x00

0x0439

VDDIO_CFG

VDDIO_CFG register

0x01

0x043C

BTSE_RESERVED_n[9]

BTSE_RESERVED_n register

0x0000 0000

2

 

Block : STANDBY_SETTINGS

Address

Name

Description

Reset

0x0460

CSI2_DATA_RATE

CSI2_DATA_RATE register

0x3B9A CA00

0x0464

CSI2_VIRTUAL_CHANNEL

CSI2_VIRTUAL_CHANNEL register

0x00

0x0465

CSI2_ISL_DATA_TYPE

CSI2_ISL_DATA_TYPE register

0x12

0x0466

CSI2_FRAME_DATA_TYPE

CSI2_FRAME_DATA_TYPE register

0x2A

0x0467

DPHY_PLL_SSCG_MODE

DPHY_PLL_SSCG_MODE register

0x00

0x0468

DPHY_PLL_SSCG_MOD_PERIOD

DPHY_PLL_SSCG_MOD_PERIOD register

0x0000

0x046A

DPHY_PLL_SSCG_INC_STEP

DPHY_PLL_SSCG_INC_STEP register

0x0000

0x046C

RANGING_FREQ

RANGING_FREQ register

0x07D0

0x0470

RANGING_PLL_SSCG_MODE

RANGING_PLL_SSCG_MODE register

0x02

0x0474

RANGING_PLL_SSCG_FREQ

RANGING_PLL_SSCG_FREQ register

0x07D0

0x0476

RANGING_PLL_SSCG_DEPTH

RANGING_PLL_SSCG_DEPTH register

0x07D0

0x0478

RANGING_PLL_SSCG_RAND

RANGING_PLL_SSCG_RAND register

0x0000

0x047A

CONTEXT_SELECTION

CONTEXT_SELECTION register

0x00

0x047B

MODE

MODE register

0x00

0x047C

SYNCHRO

SYNCHRO register

0x02

0x047D

FORMAT

FORMAT register

0x01

0x0480

FRAME_PERIOD

FRAME_PERIOD register

0x0000 80E8

0x0484

OUTPUT_IF

OUTPUT_IF register

0x00

0x0486

CSI2_FRAME_WIDTH

CSI2_FRAME_WIDTH register

0x006C

0x0488

CSI2_FRAME_HEIGHT

CSI2_FRAME_HEIGHT register

0x007E

0x048A

FRAME_SIGNALING_MODE

FRAME_SIGNALING_MODE register

0x00

0x048B

INTR_OUTPUT_MODE

INTR_OUTPUT_MODE register

0x00

0x048C

POWER_MODE

POWER_MODE register

0x00

0x048E

RESERVED1

RESERVED1 register

0x0000

0x0490

RESERVED2

RESERVED2 register

0x0000

0x0492

OTP_ADDRESS

OTP_ADDRESS register

0x0000

0x0494

OTP_SIZE

OTP_SIZE register

0x0000

0x0496

CAL_REF_OFFSET

CAL_REF_OFFSET register

0x00

0x0497

CAL_RTN_OFFSET

CAL_RTN_OFFSET register

0x20

0x0498

CAL_PROG_OFFSET_1_TO_5

CAL_PROG_OFFSET_1_TO_5 register

0x0000

0x049A

CAL_PROG_OFFSET_6

CAL_PROG_OFFSET_6 register

0x0004

0x049C

CAL_TARGET_LD

CAL_TARGET_LD register

0x0000

0x049E

HISTO_BIN_START

HISTO_BIN_START register

0x00

0x049F

HISTO_BIN_STOP

HISTO_BIN_STOP register

0x1F

0x04A0

HISTO_BIN_WIDTH

HISTO_BIN_WIDTH register

0x00

0x04A4

CROP_PARAMS

CROP_PARAMS register

0x0000 0000

0x04A8

SBSE_RESERVED_n[7]

SBSE_RESERVED_n register

0x0000 0000

2

 

Block : STANDBY_CONTEXT_SHORT

Address

Name

Description

Reset

0x04C4

BINNING

BINNING register

0x02

0x04C5

DSS_MODE

DSS_MODE register

0x02

0x04C6

REPEAT

REPEAT register

0x00

0x04C7

SBCS_RESERVED

SBCS_RESERVED register

0x00

2

 

Block : STANDBY_CONTEXT_LONG

Address

Name

Description

Reset

0x04C8

BINNING

BINNING register

0x02

0x04C9

DSS_MODE

DSS_MODE register

0x01

0x04CA

REPEAT

REPEAT register

0x00

0x04CB

SBCL_RESERVED

SBCL_RESERVED register

0x00

2

 

Block : STREAM_CONTEXT_SHORT

Address

Name

Description

Reset

0x04CC

STEP_NUMBER

STEP_NUMBER register

0x07

0x04CD

VCSEL_CONFIG_CH0_STEP_n[8]

VCSEL_CONFIG_CH0_STEP_n register

0x20

0x04D5

VCSEL_CONFIG_CH1_STEP_n[8]

VCSEL_CONFIG_CH1_STEP_n register

0x20

0x04DE

BLANKING_STEP_n[8]

BLANKING_STEP_n register

0x0000

0x04EE

MAX_DITHERING_STEP_n[8]

MAX_DITHERING_STEP_n register

0x00

0x04F6

PULSE_WIDTH_SHORT

PULSE_WIDTH_SHORT register

0x15

0x04F7

PULSE_WIDTH_LONG

PULSE_WIDTH_LONG register

0x15

0x04F8

DISTANCE_REF_LONG_OFFSET

DISTANCE_REF_LONG_OFFSET register

0x60

0x04F9

DISTANCE_RTN_LONG_OFFSET

DISTANCE_RTN_LONG_OFFSET register

0x00

0x04FA

DISTANCE_RTN_SHORT_OFFSET

DISTANCE_RTN_SHORT_OFFSET register

0x00

0x04FC

DISTANCE_SWITCHOVER

DISTANCE_SWITCHOVER register

0x0145

0x04FE

DST_SCL

DST_SCL register

0x0257

0x0500

NB_SHOT_STEP_n[8]

NB_SHOT_STEP_n register

0x0000 0000

0x0520

GROUP_HOLD

GROUP_HOLD register

0x00

0x0524

SRCS_RESERVED_n[10]

SRCS_RESERVED_n register

0x0000 0000

2

 

Block : STREAM_CONTEXT_LONG

Address

Name

Description

Reset

0x054C

STEP_NUMBER

STEP_NUMBER register

0x06

0x054D

VCSEL_CONFIG_CH0_STEP_n[8]

VCSEL_CONFIG_CH0_STEP_n register

0x20

0x0555

VCSEL_CONFIG_CH1_STEP_n[8]

VCSEL_CONFIG_CH1_STEP_n register

0x20

0x055E

BLANKING_STEP_n[8]

BLANKING_STEP_n register

0x0000

0x056E

MAX_DITHERING_STEP_n[8]

MAX_DITHERING_STEP_n register

0x00

0x0576

PULSE_WIDTH_SHORT

PULSE_WIDTH_SHORT register

0x2A

0x0577

PULSE_WIDTH_LONG

PULSE_WIDTH_LONG register

0x2A

0x0578

DISTANCE_REF_LONG_OFFSET

DISTANCE_REF_LONG_OFFSET register

0x60

0x0579

DISTANCE_RTN_LONG_OFFSET

DISTANCE_RTN_LONG_OFFSET register

0x00

0x057A

DISTANCE_RTN_SHORT_OFFSET

DISTANCE_RTN_SHORT_OFFSET register

0x02

0x057C

DISTANCE_SWITCHOVER

DISTANCE_SWITCHOVER register

0x028A

0x057E

DST_SCL

DST_SCL register

0x0256

0x0580

NB_SHOT_STEP_n[8]

NB_SHOT_STEP_n register

0x0000 0000

0x05A0

GROUP_HOLD

GROUP_HOLD register

0x00

0x05A4

SRCL_RESERVED_n[10]

SRCL_RESERVED_n register

0x0000 0000

2

 

Block : DEBUG_SETTINGS

Address

Name

Description

Reset

0x05D4

LDD_FW_BYPASS

LDD_FW_BYPASS register

0x00

0x05D5

INTENSITY_SPAD_SELECT

INTENSITY_SPAD_SELECT register

0x04

0x05D6

DSS_DEFAULT_INIT_LUT

DSS_DEFAULT_INIT_LUT register

0x03

0x05D8

SHORT_DSS_OR_TREE_LIMIT

SHORT_DSS_OR_TREE_LIMIT register

0x0000 01F4

0x05DC

SHORT_DSS_RATE_SWITCH_LO

SHORT_DSS_RATE_SWITCH_LO register

0x0000 0000

0x05E0

SHORT_DSS_RATE_SWITCH_HI

SHORT_DSS_RATE_SWITCH_HI register

0x0000 0000

0x05E4

SHORT_DSS_AMB_WEIGHT

SHORT_DSS_AMB_WEIGHT register

0x08

0x05E5

SHORT_DSS_RATE_GAIN

SHORT_DSS_RATE_GAIN register

0x15

0x05E6

SHORT_DSS_COEF_n[10]

SHORT_DSS_COEF_n register

0x0000

0x05FA

SHORT_DSS_INDEX_NB

SHORT_DSS_INDEX_NB register

0x07

0x05FB

SHORT_DSS_LUT_n[40]

SHORT_DSS_LUT_n register

0x00

0x0624

SHORT_DSS_EFF_SPAD_n[10]

SHORT_DSS_EFF_SPAD_n register

0x0000

0x0638

DBSE_RESERVED0_n[30]

DBSE_RESERVED0_n register

0x00

0x0658

LONG_DSS_OR_TREE_LIMIT

LONG_DSS_OR_TREE_LIMIT register

0x0000 01F4

0x065C

LONG_DSS_RATE_SWITCH_LO

LONG_DSS_RATE_SWITCH_LO register

0x0000 0000

0x0660

LONG_DSS_RATE_SWITCH_HI

LONG_DSS_RATE_SWITCH_HI register

0x0000 0000

0x0664

LONG_DSS_AMB_WEIGHT

LONG_DSS_AMB_WEIGHT register

0x08

0x0665

LONG_DSS_RATE_GAIN

LONG_DSS_RATE_GAIN register

0x15

0x0666

LONG_DSS_COEF_n[10]

LONG_DSS_COEF_n register

0x0000

0x067A

LONG_DSS_INDEX_NB

LONG_DSS_INDEX_NB register

0x07

0x067B

LONG_DSS_LUT_n[40]

LONG_DSS_LUT_n register

0x00

0x06A4

LONG_DSS_EFF_SPAD_n[10]

LONG_DSS_EFF_SPAD_n register

0x0000

0x06B8

DBSE_RESERVED1_n[29]

DBSE_RESERVED1_n register

0x00

0x06D5

CALIBRATION_DISABLE

CALIBRATION_DISABLE register

0x00

0x06D6

LINEAR_COMPENS_CH1

LINEAR_COMPENS_CH1 register

0x02

0x06D7

LINEAR_COMPENS_CH2

LINEAR_COMPENS_CH2 register

0x02

0x06D8

DBSE_RESERVED2_n[4]

DBSE_RESERVED2_n register

0x0000 0000

2

 

Block : OTP_MIRROR

Address

Name

Description

Reset

0x06E8

NVM_MODULE_ID

NVM_MODULE_ID register

0x0000 0000

0x06EC

GLOBAL_DISTANCE_OFFSET

GLOBAL_DISTANCE_OFFSET register

0x0000

0x06EE

OTP1_RESERVED0

OTP1_RESERVED0 register

0x0000

0x06F0

DISTANCE_OFFSET_0_n[945]

DISTANCE_OFFSET_0_n register

0x00

0x0AA1

OTP1_RESERVED1_n[15]

OTP1_RESERVED1_n register

0x00

0x0AB0

DSS_LUT_n[40]

DSS_LUT_n register

0x00

0x0AD8

OTP1_RESERVED2_n[8]

OTP1_RESERVED2_n register

0x00

0x0AE0

DEFECT_SPAD_n[20]

DEFECT_SPAD_n register

0x0000

0x0B08

OPTICAL_OFFSET_X

OPTICAL_OFFSET_X register

0x00

0x0B09

OPTICAL_OFFSET_Y

OPTICAL_OFFSET_Y register

0x00

0x0B0A

RESIDUAL_OFFSET_X

RESIDUAL_OFFSET_X register

0x00

0x0B0B

RESIDUAL_OFFSET_Y

RESIDUAL_OFFSET_Y register

0x00

0x0B0C

CAL_TEMP_DEGC

CAL_TEMP_DEGC register

0x00

0x0B0D

TEMP_SENSOR_VALUE

TEMP_SENSOR_VALUE register

0x00

0x0B0E

OTP1_RESERVED3_n[2]

OTP1_RESERVED3_n register

0x00

0x0B10

AUTO_VHV_TRIM_VOLTAGE

AUTO_VHV_TRIM_VOLTAGE register

0x0000

0x0B12

AUTO_VHV_TRIM_TEMP

AUTO_VHV_TRIM_TEMP register

0x00

0x0B14

BG_TRIM_IBIAS

BG_TRIM_IBIAS register

0x00

0x0B15

BG_TRIM_VREF

BG_TRIM_VREF register

0x00

0x0B16

TEMP_TO_DAC_GAIN

TEMP_TO_DAC_GAIN register

0x0000

0x0B18

AUTO_VHV_IDAC_SEL_FMT

AUTO_VHV_IDAC_SEL_FMT register

0x00

0x0B19

AUTO_VHV_TEMP_FMT

AUTO_VHV_TEMP_FMT register

0x00

0x0B1A

OTP1_RESERVED4

OTP1_RESERVED4 register

0x00

0x0B1B

TEMP_TO_DAC_OFFSET

TEMP_TO_DAC_OFFSET register

0x00

0x0B1C

REF_ARRAY_CHECK

REF_ARRAY_CHECK register

0x0000 0000

0x0B20

REF_ARRAY_SPAD_EN

REF_ARRAY_SPAD_EN register

0x0000 0000

0x0B24

RAD2PERP_FOV_GAIN

RAD2PERP_FOV_GAIN register

0x00

0x0B25

OTP1_RESERVED5_n[3]

OTP1_RESERVED5_n register

0x00

0x0B28

DISTANCE_OFFSET_30_n[315]

DISTANCE_OFFSET_30_n register

0x00

0x0C63

OTP1_RESERVED6_n[29]

OTP1_RESERVED6_n register

0x00

0x0C80

CAL_AMP_COEFF_n[35]

CAL_AMP_COEFF_n register

0x00

0x0CA3

CAL_AMP_SCALER

CAL_AMP_SCALER register

0x00

0x0CA4

CAL_AMP_DISTANCE

CAL_AMP_DISTANCE register

0x0000

0x0CA6

CAL_AMP_EXPO

CAL_AMP_EXPO register

0x0000

0x0CA8

CAL_AMP_REFLECTANCE

CAL_AMP_REFLECTANCE register

0x00

0x0CA9

OTP1_RESERVED7_n[11]

OTP1_RESERVED7_n register

0x00

0x0CB4

TEST_ENGI_DATA_n[13]

TEST_ENGI_DATA_n register

0x0000 0000

2

 

Block : CUSTOM_OTP_MIRROR

Address

Name

Description

Reset

0x0CE8

I2C_SLAVE_ID

I2C_SLAVE_ID register

0x00

0x0CE9

COTP_RESERVED0_n[3]

COTP_RESERVED0_n register

0x00

0x0CEC

I3C_INSTANCE_ID

I3C_INSTANCE_ID register

0x00

0x0CED

COTP_RESERVED1_n[43]

COTP_RESERVED1_n register

0x00

2

 

Block : OTP_MIRROR_SECTION2

Address

Name

Description

Reset

0x0D18

DISTANCE_OFFSET_40_n[441]

DISTANCE_OFFSET_40_n register

0x00

0x0ED1

OTP2_RESERVED0_n[23]

OTP2_RESERVED0_n register

0x00

2

 

Block : SOC_I3C

Address

Name

Description

Reset

0xD208

SOC_I3C_DEVICEID

DeviceID Control register

0x2900 0100

0xD238

SOC_I3C_PID_INST_ID

Instance ID value of device PID

0x0000 0000

2

 

Block : SOC_CABDT

Address

Name

Description

Reset

0xD520

SOC_CABDT_ALGO_SCALE

ALGO_SCALE register

0x0000 0000

0xD524

SOC_CABDT_DIST_SCALE

DIST_SCALE register

0x0000 0000

2


Block: REVISION_STATUS

Description

 :

3

 

Register: DEVICE_MODEL_ID

Description

 : DEVICE_MODEL_ID register

Offset

 : 0x0

Absolute Address

 : 0x0000

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x5333 4C39

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x5333 4C39

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

Device identification in ASCII (S3L9)

RO

-

-

0x5333 4C39

6

 

Register: DEVICE_REVISION

Description

 : DEVICE_REVISION register

Offset

 : 0x4

Absolute Address

 : 0x0004

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

LOGIC_FE_REVISION

LOGIC_BE_REVISION

RO - 0x0A

RO - 0x00

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FE_REVISION

BE_REVISION

OPTICAL_REVISION

RO - 0xA

RO - 0x0

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:24

LOGIC_FE_REVISION

C40 die front end revision

RO

-

-

0x0A

23:16

LOGIC_BE_REVISION

C40 die back end revision

RO

-

-

0x00

15:12

FE_REVISION

Front end revision from Mask Code (HW)

RO

-

-

0xA

11:8

BE_REVISION

Back End revision from Mask Code (HW)

RO

-

-

0x0

7:0

OPTICAL_REVISION

Optical revision from NVM tracability (optional)

RO

-

-

0x00

6

 

Register: UI_REVISION

Description

 : UI_REVISION register

Offset

 : 0x8

Absolute Address

 : 0x0008

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MAJOR

MINOR

RO - 0x02

RO - 0x04

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:8

MAJOR

Major UI revision

RO

-

-

0x02

7:0

MINOR

Minor UI revision

RO

-

-

0x04

6

 

Register: ROM_REVISION

Description

 : ROM_REVISION register

Offset

 : 0xA

Absolute Address

 : 0x000A

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MAJOR

MINOR

RO - 0x00

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:8

MAJOR

Major ROM code revision

RO

-

-

0x00

7:0

MINOR

Minor ROM code revision

RO

-

-

0x00

6

 

Register: PATCH_REVISION

Description

 : PATCH_REVISION register

Offset

 : 0xC

Absolute Address

 : 0x000C

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MAJOR

MINOR

RO - 0x00

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:8

MAJOR

Major FWP revision

RO

-

-

0x00

7:0

MINOR

Minor FWP revision

RO

-

-

0x00

6

 

Register: ROM_MD5_n[4]

Description

 : ROM_MD5_n register

Offset

 : [0x10 - 0x1C]

Absolute Address

 : [0x0010 - 0x001C]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

ROM MD5 signature

RO

-

-

0x0000 0000

6

 

Register: RVST_RESERVED_n[2]

Description

 : RVST_RESERVED_n register

Offset

 : [0x20 - 0x24]

Absolute Address

 : [0x0020 - 0x0024]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RO

-

-

0x0000 0000

6


Block: SENSOR_STATUS

Description

 :

3

 

Register: FRAME_COUNTER

Description

 : FRAME_COUNTER register

Offset

 : 0x0

Absolute Address

 : 0x0028

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

Frame number

RO

-

-

0x0000 0000

6

 

Register: TEMPERATURE

Description

 : TEMPERATURE register

Offset

 : 0x4

Absolute Address

 : 0x002C

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Device temperature (signed from -40 to 150°C)

RO

-

-

0x0000

6

 

Register: LDD_TEMPERATURE

Description

 : LDD_TEMPERATURE register

Offset

 : 0x6

Absolute Address

 : 0x002E

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Laser driver temperature

RO

-

-

0x0000

6

 

Register: LDD_POWER_CH0_n[7]

Description

 : LDD_POWER_CH0_n register

Offset

 : [0x8 - 0x14]

Absolute Address

 : [0x0030 - 0x003C]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Channel 0 Laser driver power for each step

RO

-

-

0x0000

6

 

Register: LDD_POWER_CH1_n[7]

Description

 : LDD_POWER_CH1_n register

Offset

 : [0x16 - 0x22]

Absolute Address

 : [0x003E - 0x004A]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Channel 1 Laser driver power for each step

RO

-

-

0x0000

6

 

Register: REF_LONG_ST_CH1

Description

 : REF_LONG_ST_CH1 register

Offset

 : 0x24

Absolute Address

 : 0x004C

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

DISTANCE

RO - 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AMPLITUDE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:16

DISTANCE

Reference array long step channel 1 distance

RO

-

-

0x0000

15:0

AMPLITUDE

Reference array long step channel 1 amplitude

RO

-

-

0x0000

6

 

Register: REF_LONG_ST_CH2

Description

 : REF_LONG_ST_CH2 register

Offset

 : 0x28

Absolute Address

 : 0x0050

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

DISTANCE

RO - 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AMPLITUDE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:16

DISTANCE

Reference array long step channel 2 distance

RO

-

-

0x0000

15:0

AMPLITUDE

Reference array long step channel 2 amplitude

RO

-

-

0x0000

6

 

Register: REF_SHORT_ST_CH1

Description

 : REF_SHORT_ST_CH1 register

Offset

 : 0x2C

Absolute Address

 : 0x0054

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

DISTANCE

RO - 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AMPLITUDE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:16

DISTANCE

Reference array short step channel 1 distance

RO

-

-

0x0000

15:0

AMPLITUDE

Reference array short step channel 1 amplitude

RO

-

-

0x0000

6

 

Register: REF_SHORT_ST_CH2

Description

 : REF_SHORT_ST_CH2 register

Offset

 : 0x30

Absolute Address

 : 0x0058

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

DISTANCE

RO - 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AMPLITUDE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:16

DISTANCE

Reference array short step channel 2 distance

RO

-

-

0x0000

15:0

AMPLITUDE

Reference array short step channel 2 amplitude

RO

-

-

0x0000

6

 

Register: CURRENT_FRAME_WIDTH

Description

 : CURRENT_FRAME_WIDTH register

Offset

 : 0x34

Absolute Address

 : 0x005C

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

current frame width

RO

-

-

0x0000

6

 

Register: CURRENT_FRAME_HEIGHT

Description

 : CURRENT_FRAME_HEIGHT register

Offset

 : 0x36

Absolute Address

 : 0x005E

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Current frame height

RO

-

-

0x0000

6

 

Register: CURRENT_STATIC_SETTINGS

Description

 : CURRENT_STATIC_SETTINGS register

Offset

 : 0x38

Absolute Address

 : 0x0060

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

MODE

FORMAT

POWER_MODE

SYNCHRO

RO - 0x0

RO - 0x0

RO - 0x0

RO - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:6

MODE

Current aquisiton mode

RO

-

-

0x0

5:4

FORMAT

Current format

RO

-

-

0x0

3:2

POWER_MODE

Current power mode

RO

-

-

0x0

1:0

SYNCHRO

Current Synchro

RO

-

-

0x0

6

 

Register: AMBIENT_ATTENUATION

Description

 : AMBIENT_ATTENUATION register

Offset

 : 0x39

Absolute Address

 : 0x0061

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RO - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

3:0

VALUE

Ambient Attenuation: copy of ALGO_SCALE.AMB_ATT CABDT register

RO

-

-

0x0

6

 

Register: CURRENT_DYNAMIC_SETTINGS

Description

 : CURRENT_DYNAMIC_SETTINGS register

Offset

 : 0x3A

Absolute Address

 : 0x0062

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

STEP_NUMBER

CONTEXT

BINNING

DSS_MODE

 

RO - 0x0

RO - 0x0

RO - 0x00

RO - 0x0

 

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:12

STEP_NUMBER

Current Number of Steps

RO

-

-

0x0

11

CONTEXT

Current Context

RO

-

-

0x0

10:6

BINNING

Current binning

RO

-

-

0x00

5:4

DSS_MODE

Current DSS mode

RO

-

-

0x0

6

 

Register: ERROR_CODE

Description

 : ERROR_CODE register

Offset

 : 0x3C

Absolute Address

 : 0x0064

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Firmware error code

        0x0000 TOP_ERROR_NO_ERROR

        0x0001 TOP_ERROR_UI

        0x0002 TOP_ERROR_STREAMING

        0x0003 TOP_ERROR_DSS_TIMEOUT

        0x0004 TOP_ERROR_SYSTEM_FAULT

        0x0005 TOP_ERROR_ADDR_MONITOR

        0x0006 TOP_ERROR_OIF

        0x0007 TOP_ERROR_UI_DSS

        0x0008 TOP_ERROR_LDD_TIMEOUT

        0x0009 TOP_ERROR_LDD_NULL_PTR

        0x000a TOP_ERROR_LDD_SPI

        0x000b TOP_ERROR_LDD_OTP_CRC

        0x000c TOP_ERROR_LDD_NULL_SIZE

        0x000d TOP_ERROR_LDD_SAFETY

        0x000e TOP_ERROR_UI_CROP

        0x0200 WINDOWING_ERROR_VERSION

        0x0201 WINDOWING_ERROR_ROLLOVER

        0x0202 WINDOWING_ERROR_OVERLAP

        0x0203 WINDOWING_ERROR_LOCK

        0x0300 DPHYTXCADENCE_ERROR_ULPS_ENTER_TIMEOUT

        0x0301 DPHYTXCADENCE_ERROR_ULPS_EXIT_TIMEOUT

        0x0400 THERMALSENSOR_ERROR_TIMEOUT

        0x0401 THERMALSENSOR_ERROR_DATAREADY

        0x0500 SPI2S3_ERROR_TIMEOUT

        0x0501 SPI2S3_ERROR_SPI_CLOCK

        0x0502 SPI2S3_ERROR_NO_SLAVE

        0x0503 SPI2S3_ERROR_FLASH_NOT_PRESENT

        0x0504 SPI2S3_ERROR_FLASH_READ_ID

        0x0505 SPI2S3_ERROR_FLASH_READ_STATUS

        0x0506 SPI2S3_ERROR_FLASH_ERASE

        0x0507 SPI2S3_ERROR_FLASH_READ

        0x0508 SPI2S3_ERROR_FLASH_WRITE

        0x0509 SPI2S3_ERROR_FLASH_VERIFY

        0x050a SPI2S3_ERROR_FLASH_WRITE_ENABLE

        0x050b SPI2S3_ERROR_FLASH_WRITE_DISABLE

        0x050c SPI2S3_ERROR_INTERRUPT_MODFIE_NOT_SET

        0x050d SPI2S3_ERROR_INTERRUPT_TIFREIE_NOT_SET

        0x050e SPI2S3_ERROR_INTERRUPT_CRCIE_NOT_SET

        0x050f SPI2S3_ERROR_INTERRUPT_OVRIE_NOT_SET

        0x0510 SPI2S3_ERROR_INTERRUPT_UDRIE_NOT_SET

        0x0511 SPI2S3_ERROR_INTERRUPT_TXTFIE_NOT_SET

        0x0512 SPI2S3_ERROR_INTERRUPT_EOTIE_NOT_SET

        0x0513 SPI2S3_ERROR_INTERRUPT_DXPIE_NOT_SET

        0x0514 SPI2S3_ERROR_INTERRUPT_TXPIE_NOT_SET

        0x0515 SPI2S3_ERROR_INTERRUPT_RXPIE_NOT_SET

        0x0516 SPI2S3_ERROR_INTERRUPT_SUSPC_NOT_CLEAR

        0x0517 SPI2S3_ERROR_INTERRUPT_MODFC_NOT_CLEAR

        0x0518 SPI2S3_ERROR_INTERRUPT_TIFREC_NOT_CLEAR

        0x0519 SPI2S3_ERROR_INTERRUPT_CRCEC_NOT_CLEAR

        0x051a SPI2S3_ERROR_INTERRUPT_OVRC_NOT_CLEAR

        0x051b SPI2S3_ERROR_INTERRUPT_UDRC_NOT_CLEAR

        0x051c SPI2S3_ERROR_INTERRUPT_TXTFC_NOT_CLEAR

        0x051d SPI2S3_ERROR_INTERRUPT_EOTC_NOT_CLEAR

        0x0600 CLKCHANGER_ERROR_VERSION

        0x0800 ISLGEN2_ERROR_VERSION

        0x0801 ISLGEN2_ERROR_INVALID_CFG

        0x0802 ISLGEN2_ERROR_MISSED_TRIGGER

        0x0803 ISLGEN2_ERROR_TOO_MANY_ENTRIES

        0x0804 ISLGEN2_ERROR_MEMORY_LOCKED

        0x0900 CSI2TX_ERROR_VERSION

        0x0901 CSI2TX_ERROR_PKT_TOO_LONG

        0x0902 CSI2TX_ERROR_PKT_TOO_SHORT

        0x0903 CSI2TX_ERROR_UNDERFLOW

        0x0904 CSI2TX_ERROR_LANE_DESYNC

        0x0a00 NVM_ERROR_READ_CORRECTED_ECC

        0x0a01 NVM_ERROR_CLK_FREQ

        0x0a02 NVM_ERROR_NULL_PTR

        0x0a03 NVM_ERROR_ADDRESS_TOO_FAR

        0x0a04 NVM_ERROR_SIZE_TOO_BIG

        0x0a05 NVM_ERROR_READ_TIMEOUT

        0x0a06 NVM_ERROR_READ_ECC_FAIL

        0x0a07 NVM_ERROR_WRITE_TIMEOUT

        0x0a08 NVM_ERROR_WRITE_FAIL

        0x0a09 NVM_ERROR_PROG_ON_NON_VIRGIN_WORD

        0x0b00 FRAMEMERGER_ERROR_VERSION

        0x0c00 I3CSLAVELITE_ERROR_VERSION

        0x0e00 STATSDATAFETCHER_ERROR_FETCHING

        0x0e01 STATSDATAFETCHER_ERROR_RDCMD_NB

        0x0f00 CABDT_ERROR_LDD_FAULT

        0x0f01 CABDT_ERROR_FRAME_REQ

        0x0f02 CABDT_ERROR_FSM_STEP

        0x0f03 CABDT_ERROR_NULL_PTR

        0x0f04 CABDT_ERROR_CONFIG

        0x0f05 CABDT_ERROR_VHV_TIMEOUT

        0x0f06 CABDT_ERROR_DSS_TIMEOUT

        0x1000 CRM_ERROR_TOFPLL_LOCK_TIMEOUT

        0x1001 CRM_ERROR_PHYPLL_LOCK_TIMEOUT

        0x1002 CRM_ERROR_INVALID_CONFIG

        0x1003 CRM_ERROR_INVALID_RATIO

        0x1004 CRM_ERROR_PHYPLL_EXT_CLK

        0x1005 CRM_ERROR_PHYPLL_VCO_RANGE

        0x1006 CRM_ERROR_PHYPLL_MULT_RANGE

        0x1007 CRM_ERROR_LDO_TIMEOUT

        0x1008 CRM_ERROR_BG_TIMEOUT

        0x1009 CRM_ERROR_INVALID_EXT_CLOCK_FREQ

        0x1300 PATCH_ERROR_PATCH_CODE_TOO_LARGE

        0x1301 PATCH_ERROR_TOO_MANY_PATCHES

        0x1302 PATCH_ERROR_TOO_MANY_HOOKS

        0x1303 PATCH_ERROR_BAD_CRC

        0x1304 PATCH_ERROR_BAD_PATCH_ADDR

        0x1305 PATCH_ERROR_BAD_MD5SUM

RO

-

-

0x0000

6

 

Register: ERROR_STATUS

Description

 : ERROR_STATUS register

Offset

 : 0x3E

Absolute Address

 : 0x0066

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

FW_ERROR

REF_ARRAY

PLL_LOCK

SOF_OUTSIDE_BLANKING

I_LIMIT

SPAD_SUPPLY_OVERLOAD

VHV_UNDERVOLTAGE

VHV_OVERVOLTAGE

RO - 0x0

RO - 0x0

RO - 0x0

RO - 0x0

RO - 0x0

RO - 0x0

RO - 0x0

RO - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7

FW_ERROR

Internal FW error, check ERROR_CODE for detail

RO

-

-

0x0

6

REF_ARRAY

Reference array check status

RO

-

-

0x0

5

PLL_LOCK

PLL lock error status

RO

-

-

0x0

4

SOF_OUTSIDE_BLANKING

SOF outside blanking error status

RO

-

-

0x0

3

I_LIMIT

HVBOOST I limit status

RO

-

-

0x0

2

SPAD_SUPPLY_OVERLOAD

SPAD supply overload status

RO

-

-

0x0

1

VHV_UNDERVOLTAGE

VHV monitoring undervoltage error status

RO

-

-

0x0

0

VHV_OVERVOLTAGE

VHV monitoring overvoltage error status

RO

-

-

0x0

6

 

Register: LDD_ERROR_STATUS_n[5]

Description

 : LDD_ERROR_STATUS_n register

Offset

 : [0x3F - 0x43]

Absolute Address

 : [0x0067 - 0x006B]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Error status returned by the Laser driver when receiving Fault

RO

-

-

0x00

6

 

Register: CURRENT_FRAME_PERIOD

Description

 : CURRENT_FRAME_PERIOD register

Offset

 : 0x44

Absolute Address

 : 0x006C

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

Current frame period

RO

-

-

0x0000 0000

6

 

Register: CROP_DSS_STATUS

Description

 : CROP_DSS_STATUS register

Offset

 : 0x48

Absolute Address

 : 0x0070

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

DEFAULT_DSS_LUT

CROP_ENABLE

CROP_Y_OFF_STAT

CROP_X_OFF_STAT

 

RO - 0x0

RO - 0x0

RO - 0x00

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CROP_X_OFF_STAT

CROP_Y_SIZE_STAT

CROP_X_SIZE_STAT

RO - 0x00

RO - 0x00

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

28:25

DEFAULT_DSS_LUT

LUT used when DSS disabled

RO

-

-

0x0

24

CROP_ENABLE

Enable bit of crop

RO

-

-

0x0

23:18

CROP_Y_OFF_STAT

Y offset from 0,0 output picture of crop in Zone unit

RO

-

-

0x00

17:12

CROP_X_OFF_STAT

X offset from 0,0 output picture of crop in Zone unit

RO

-

-

0x00

11:6

CROP_Y_SIZE_STAT

Y size of crop in Zone unit

RO

-

-

0x00

5:0

CROP_X_SIZE_STAT

X size of crop in Zone unit

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_1_LSB

Description

 : NB_SHOT_STEP_1_LSB register

Offset

 : 0x4C

Absolute Address

 : 0x0074

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 1 LSB

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_1_MID

Description

 : NB_SHOT_STEP_1_MID register

Offset

 : 0x4D

Absolute Address

 : 0x0075

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 1 Middle

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_1_MSB

Description

 : NB_SHOT_STEP_1_MSB register

Offset

 : 0x4E

Absolute Address

 : 0x0076

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 1 MSB

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_4_5_LSB

Description

 : NB_SHOT_STEP_4_5_LSB register

Offset

 : 0x4F

Absolute Address

 : 0x0077

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 4/5 LSB

Step4 for 6 steps mode

Step5 for 7 steps mode

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_4_5_MID

Description

 : NB_SHOT_STEP_4_5_MID register

Offset

 : 0x50

Absolute Address

 : 0x0078

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 4/5 Middle

Step4 for 6 steps mode

Step5 for 7 steps mode

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_4_5_MSB

Description

 : NB_SHOT_STEP_4_5_MSB register

Offset

 : 0x51

Absolute Address

 : 0x0079

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 4/5 MSB

Step4 for 6 steps mode

Step5 for 7 steps mode

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_6_LSB

Description

 : NB_SHOT_STEP_6_LSB register

Offset

 : 0x52

Absolute Address

 : 0x007A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 6 LSB

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_6_MID

Description

 : NB_SHOT_STEP_6_MID register

Offset

 : 0x53

Absolute Address

 : 0x007B

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 6 Middle

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_6_MSB

Description

 : NB_SHOT_STEP_6_MSB register

Offset

 : 0x54

Absolute Address

 : 0x007C

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 6 MSB

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_7_LSB

Description

 : NB_SHOT_STEP_7_LSB register

Offset

 : 0x55

Absolute Address

 : 0x007D

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 7 LSB

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_7_MID

Description

 : NB_SHOT_STEP_7_MID register

Offset

 : 0x56

Absolute Address

 : 0x007E

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 7 Middle

RO

-

-

0x00

6

 

Register: NB_SHOT_STEP_7_MSB

Description

 : NB_SHOT_STEP_7_MSB register

Offset

 : 0x57

Absolute Address

 : 0x007F

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Number of Shots for Step 7 MSB

RO

-

-

0x00

6

 

Register: SEST_RESERVED_n[3]

Description

 : SEST_RESERVED_n register

Offset

 : [0x58 - 0x60]

Absolute Address

 : [0x0080 - 0x0088]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RO

-

-

0x0000 0000

6


Block: FW_STATUS

Description

 :

3

 

Register: SYSTEM_FSM

Description

 : SYSTEM_FSM register

Offset

 : 0x0

Absolute Address

 : 0x008C

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Sensor system FSM status:

        0x00 FSM_NONE: FSM_NONE

        0x01 FSM_READY_TO_BOOT: FSM_READY_TO_BOOT

        0x02 FSM_STANDBY: FSM_STANDBY

        0x03 FSM_STREAMING: FSM_STREAMING

RO

-

-

0x00

6

 

Register: COMMAND_ERROR

Description

 : COMMAND_ERROR register

Offset

 : 0x1

Absolute Address

 : 0x008D

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Sensor system FSM status:

        0x00 CMD_ERROR_NONE: CMD_ERROR_NONE

        0x01 CMD_ERROR_FORBIDDEN: CMD_ERROR_FORBIDDEN

        0x02 CMD_ERROR_INVALID: CMD_ERROR_INVALID

RO

-

-

0x00

6

 

Register: FRAME_READY

Description

 : FRAME_READY register

Offset

 : 0x2

Absolute Address

 : 0x008E

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RO - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

0

VALUE

Frame is ready to acces through I3C

RO

-

-

0x0

6

 

Register: XSTART

Description

 : XSTART register

Offset

 : 0x3

Absolute Address

 : 0x008F

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Xstart computed by FW

RO

-

-

0x00

6

 

Register: YSTART

Description

 : YSTART register

Offset

 : 0x4

Absolute Address

 : 0x0090

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Ystart computed by FW

RO

-

-

0x00

6

 

Register: FINAL_WIDTH

Description

 : FINAL_WIDTH register

Offset

 : 0x5

Absolute Address

 : 0x0091

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Image width after binning

RO

-

-

0x00

6

 

Register: FINAL_HEIGHT

Description

 : FINAL_HEIGHT register

Offset

 : 0x6

Absolute Address

 : 0x0092

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RO - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Image height after binning

RO

-

-

0x00

6

 

Register: FWST_RESERVED_n[10]

Description

 : FWST_RESERVED_n register

Offset

 : [0x8 - 0x2C]

Absolute Address

 : [0x0094 - 0x00B8]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RO - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RO - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RO

-

-

0x0000 0000

6


Block: CONTROL

Description

 :

3

 

Register: COMMAND

Description

 : COMMAND register

Offset

 : 0x0

Absolute Address

 : 0x0400

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

 

        0x00 CMD_NONE: CMD_NONE

        0x01 CMD_BOOT: Request FW patch setup

        0x02 CMD_START_STREAM: Request start streaming

        0x03 CMD_STOP_STREAM: Request stop streaming

        0x04 CMD_THSENS_READ: Read thermal sensor value

        0x05 CMD_TRIGGER_NEXT_FRAME: Trigger next frame in manual mode

        0x06 CMD_ACK_FRAME_READ: Acknowledge frame read back through I3C

        0x07 CMD_SWITCH_TO_FAST_CLOCK: Turn on the PLL and switching the system clock to the fast clock

        0x08 CMD_SWITCH_TO_EXT_CLOCK: Switching the system clock to the external clock and turn off the PLL

        0x09 CMD_OTP_CUSTOM_WRITE: Write OTP Custom from OTP_CUSTOM mirror page

        0x0A CMD_DSS_LUT_MAP: Map DSS Lut buffer instead of OUT buffer

        0x0B CMD_DSS_LUT_UNMAP: Remap OUT buffer (default)

        0x0C CMD_FAST_RESTART: Stop and Restart immediately relatching static values

RW

-

-

0x00

6

 

Register: CTRL_RESERVED_n[10]

Description

 : CTRL_RESERVED_n register

Offset

 : [0x4 - 0x28]

Absolute Address

 : [0x0404 - 0x0428]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RW

-

-

0x0000 0000

6


Block: BOOT_SETTINGS

Description

 :

3

 

Register: EXT_CLOCK

Description

 : EXT_CLOCK register

Offset

 : 0x0

Absolute Address

 : 0x042C

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x00B7 1B00

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x00B7 1B00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

External clock frequency in Hz (from 6MHz to 27MHz)

RW

-

-

0x00B7 1B00

6

 

Register: INSTALL_PATCH

Description

 : INSTALL_PATCH register

Offset

 : 0x4

Absolute Address

 : 0x0430

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

0

VALUE

Flag to be set to install PATCH on BOOT command.

RW

-

-

0x0

6

 

Register: SPI_FORMAT

Description

 : SPI_FORMAT register

Offset

 : 0x5

Absolute Address

 : 0x0431

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

0

VALUE

SPI Format:

        0x00 SPI_HALF_DUPLEX: SPI_HALF_DUPLEX

        0x01 SPI_FULL_DUPLEX: SPI_FULL_DUPLEX

RW

-

-

0x0

6

 

Register: LDD_OTP_CRC

Description

 : LDD_OTP_CRC register

Offset

 : 0x8

Absolute Address

 : 0x0434

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

CRC of Laser Driver OTP

RW

-

-

0x0000 0000

6

 

Register: VDDA_CFG

Description

 : VDDA_CFG register

Offset

 : 0xC

Absolute Address

 : 0x0438

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Voltage for VDDA :

        0x0 VDDA_2_8V: VDDA_2_8V

        0x1 VDDA_3_3V: VDDA_3_3V

RW

-

-

0x00

6

 

Register: VDDIO_CFG

Description

 : VDDIO_CFG register

Offset

 : 0xD

Absolute Address

 : 0x0439

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x01

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Voltage for VDDIO :

        0x0 VDDIO_1_2V: VDDIO_1_2V

        0x1 VDDIO_1_8V: VDDIO_1_8V

RW

-

-

0x01

6

 

Register: BTSE_RESERVED_n[9]

Description

 : BTSE_RESERVED_n register

Offset

 : [0x10 - 0x30]

Absolute Address

 : [0x043C - 0x045C]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RW

-

-

0x0000 0000

6


Block: STANDBY_SETTINGS

Description

 :

3

 

Register: CSI2_DATA_RATE

Description

 : CSI2_DATA_RATE register

Offset

 : 0x0

Absolute Address

 : 0x0460

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x3B9A CA00

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x3B9A CA00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

MIPI CSI2 data rate in bit per second (100Mbps to 1Gbps)

RW

-

-

0x3B9A CA00

6

 

Register: CSI2_VIRTUAL_CHANNEL

Description

 : CSI2_VIRTUAL_CHANNEL register

Offset

 : 0x4

Absolute Address

 : 0x0464

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

ISL and data virtual channel over

RW

-

-

0x0

6

 

Register: CSI2_ISL_DATA_TYPE

Description

 : CSI2_ISL_DATA_TYPE register

Offset

 : 0x5

Absolute Address

 : 0x0465

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

FORCE_ISL_WIDTH

VALUE

 

RW - 0x0

RW - 0x12

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6

FORCE_ISL_WIDTH

if 0: ISL width is equal CSI2_FRAME_WIDTH (default)

if 1: ISL width is equal to SENSOR_STATUS page size

RW

-

-

0x0

5:0

VALUE

ISL datatype over CSI2

RW

-

-

0x12

6

 

Register: CSI2_FRAME_DATA_TYPE

Description

 : CSI2_FRAME_DATA_TYPE register

Offset

 : 0x6

Absolute Address

 : 0x0466

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x2A

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

FRAME datatype over CSI2

RW

-

-

0x2A

6

 

Register: DPHY_PLL_SSCG_MODE

Description

 : DPHY_PLL_SSCG_MODE register

Offset

 : 0x7

Absolute Address

 : 0x0467

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

DPHY PLL spread spectrum mode:

        0x00 SSCG_DISABLED: SSCG_DISABLED

        0x01 SSCG_DOWNSPREAD: SSCG_DOWNSPREAD

        0x02 SSCG_CENTERSPREAD: SSCG_CENTERSPREAD

RW

-

-

0x0

6

 

Register: DPHY_PLL_SSCG_MOD_PERIOD

Description

 : DPHY_PLL_SSCG_MOD_PERIOD register

Offset

 : 0x8

Absolute Address

 : 0x0468

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

12:0

VALUE

DPHY PLL spread spectrum modulation period

RW

-

-

0x0000

6

 

Register: DPHY_PLL_SSCG_INC_STEP

Description

 : DPHY_PLL_SSCG_INC_STEP register

Offset

 : 0xA

Absolute Address

 : 0x046A

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

DPHY PLL spread spectrum increment sptep

RW

-

-

0x0000

6

 

Register: RANGING_FREQ

Description

 : RANGING_FREQ register

Offset

 : 0xC

Absolute Address

 : 0x046C

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x07D0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Ranging frequency in MHz (from 1000 to 2000 MHz)

RW

-

-

0x07D0

6

 

Register: RANGING_PLL_SSCG_MODE

Description

 : RANGING_PLL_SSCG_MODE register

Offset

 : 0x10

Absolute Address

 : 0x0470

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x2

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Ranging PLL spread spectrum mode:

        0x01 SSCG_SINEWAVE: SSCG_SINEWAVE

        0x02 SSCG_TRIANGLE: SSCG_TRIANGLE

RW

-

-

0x2

6

 

Register: RANGING_PLL_SSCG_FREQ

Description

 : RANGING_PLL_SSCG_FREQ register

Offset

 : 0x14

Absolute Address

 : 0x0474

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x07D0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Ranging PLL spread spectrum FREQ

RW

-

-

0x07D0

6

 

Register: RANGING_PLL_SSCG_DEPTH

Description

 : RANGING_PLL_SSCG_DEPTH register

Offset

 : 0x16

Absolute Address

 : 0x0476

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x07D0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Ranging PLL spread spectrum DEPTH

RW

-

-

0x07D0

6

 

Register: RANGING_PLL_SSCG_RAND

Description

 : RANGING_PLL_SSCG_RAND register

Offset

 : 0x18

Absolute Address

 : 0x0478

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Ranging PLL spread spectrum RAND

RW

-

-

0x0000

6

 

Register: CONTEXT_SELECTION

Description

 : CONTEXT_SELECTION register

Offset

 : 0x1A

Absolute Address

 : 0x047A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Context selection:

        0x00 ALWAYS_SHORT: ALWAYS_SHORT

        0x01 ALWAYS_LONG: ALWAYS_LONG

        0x02 COMPOSITE: COMPOSITE

RW

-

-

0x0

6

 

Register: MODE

Description

 : MODE register

Offset

 : 0x1B

Absolute Address

 : 0x047B

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Operating mode:

        0x00 MODE_RANGING: MODE_RANGING

        0x01 MODE_HISTOGRAM: MODE_HISTOGRAM

        0x02 MODE_HOST_CONTROL: MODE_HOST_CONTROL

        0x03 MODE_INTENSITY: MODE_INTENSITY

RW

-

-

0x0

6

 

Register: SYNCHRO

Description

 : SYNCHRO register

Offset

 : 0x1C

Absolute Address

 : 0x047C

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x2

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Synchronization mode:

        0x00 SYNC_SLAVE: SYNC_SLAVE

        0x01 SYNC_MANUAL: SYNC_MANUAL

        0x02 SYNC_AUTONOMOUS: SYNC_AUTONOMOUS

RW

-

-

0x2

6

 

Register: FORMAT

Description

 : FORMAT register

Offset

 : 0x1D

Absolute Address

 : 0x047D

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x1

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Frame format:

        0x00 SQUARE: SQUARE

        0x01 WIDE: WIDE

        0x02 FULL: FULL

RW

-

-

0x1

6

 

Register: FRAME_PERIOD

Description

 : FRAME_PERIOD register

Offset

 : 0x20

Absolute Address

 : 0x0480

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 80E8

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 80E8

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

Frame period in us. from 10000us to 1000000 (1s).

RW

-

-

0x0000 80E8

6

 

Register: OUTPUT_IF

Description

 : OUTPUT_IF register

Offset

 : 0x24

Absolute Address

 : 0x0484

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

0

VALUE

Output interface selection:

        0x00 CSI2: CSI2

        0x01 I3C: I3C

RW

-

-

0x0

6

 

Register: CSI2_FRAME_WIDTH

Description

 : CSI2_FRAME_WIDTH register

Offset

 : 0x26

Absolute Address

 : 0x0486

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x006C

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

CSI2 Frame width (54*2 by default))

RW

-

-

0x006C

6

 

Register: CSI2_FRAME_HEIGHT

Description

 : CSI2_FRAME_HEIGHT register

Offset

 : 0x28

Absolute Address

 : 0x0488

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x007E

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

CSI2 Frame height (42*3 by default)

RW

-

-

0x007E

6

 

Register: FRAME_SIGNALING_MODE

Description

 : FRAME_SIGNALING_MODE register

Offset

 : 0x2A

Absolute Address

 : 0x048A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

0

VALUE

Frame signaling mode.

        0x00 I3C_IBI: In band interrupt in I3C, no signaling in CSI2

        0x01 INTR_PAD: INTR PAD signaling (both in I3C and CSI2)

RW

-

-

0x0

6

 

Register: INTR_OUTPUT_MODE

Description

 : INTR_OUTPUT_MODE register

Offset

 : 0x2B

Absolute Address

 : 0x048B

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

0

VALUE

INTR PAD mode:

        0x0 CMOS: CMOS

        0x1 OPEN_DRAIN: OPEN_DRAIN

RW

-

-

0x0

6

 

Register: POWER_MODE

Description

 : POWER_MODE register

Offset

 : 0x2C

Absolute Address

 : 0x048C

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Power mode selection:

        0x00 REGULAR: REGULAR

        0x01 LOW_POWER: LOW_POWER

        0x02 ULTRA_LOW_POWER: ULTRA_LOW_POWER

RW

-

-

0x0

6

 

Register: RESERVED1

Description

 : RESERVED1 register

Offset

 : 0x2E

Absolute Address

 : 0x048E

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

RESERVED

RW

-

-

0x0000

6

 

Register: RESERVED2

Description

 : RESERVED2 register

Offset

 : 0x30

Absolute Address

 : 0x0490

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

RESERVED

RW

-

-

0x0000

6

 

Register: OTP_ADDRESS

Description

 : OTP_ADDRESS register

Offset

 : 0x32

Absolute Address

 : 0x0492

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

10:0

VALUE

Address to read/write in the OTP or start address form multiple read/write

RW

-

-

0x000

6

 

Register: OTP_SIZE

Description

 : OTP_SIZE register

Offset

 : 0x34

Absolute Address

 : 0x0494

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

10:0

VALUE

Number of 32 byte word to read/write from/to OTP in multiple access.

RW

-

-

0x000

6

 

Register: CAL_REF_OFFSET

Description

 : CAL_REF_OFFSET register

Offset

 : 0x36

Absolute Address

 : 0x0496

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Reference array ranging window offset vs T0 for the calibation phase in bins

RW

-

-

0x00

6

 

Register: CAL_RTN_OFFSET

Description

 : CAL_RTN_OFFSET register

Offset

 : 0x37

Absolute Address

 : 0x0497

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x20

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Return array ranging window offset vs T0 offset for the calibation phase in bins

RW

-

-

0x20

6

 

Register: CAL_PROG_OFFSET_1_TO_5

Description

 : CAL_PROG_OFFSET_1_TO_5 register

Offset

 : 0x38

Absolute Address

 : 0x0498

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

offset applied to Laser pulse position vs Ranging windows for steps 1 to 5 (signed value) in bins/4

RW

-

-

0x0000

6

 

Register: CAL_PROG_OFFSET_6

Description

 : CAL_PROG_OFFSET_6 register

Offset

 : 0x3A

Absolute Address

 : 0x049A

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0004

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

offset applied to Laser pulse position vs Ranging windows for steps 6 (signed value) in bins/4

RW

-

-

0x0004

6

 

Register: CAL_TARGET_LD

Description

 : CAL_TARGET_LD register

Offset

 : 0x3C

Absolute Address

 : 0x049C

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Target for the laser pulse within reference windows in bins.

Used to set t_start_ldd if CALIBRATION_DISABLE == 1

RW

-

-

0x0000

6

 

Register: HISTO_BIN_START

Description

 : HISTO_BIN_START register

Offset

 : 0x3E

Absolute Address

 : 0x049E

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

1st bin to start Histogram (in bin)

RW

-

-

0x00

6

 

Register: HISTO_BIN_STOP

Description

 : HISTO_BIN_STOP register

Offset

 : 0x3F

Absolute Address

 : 0x049F

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x1F

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Last bin used in Histogram (in bin)

RW

-

-

0x1F

6

 

Register: HISTO_BIN_WIDTH

Description

 : HISTO_BIN_WIDTH register

Offset

 : 0x40

Absolute Address

 : 0x04A0

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

2:0

VALUE

bin width for Histogram. bin_width = 2^VALUE.

From 0->1ns to 4->16ns

RW

-

-

0x0

6

 

Register: CROP_PARAMS

Description

 : CROP_PARAMS register

Offset

 : 0x44

Absolute Address

 : 0x04A4

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

CROP_ENABLE

CROP_Y_OFFSET

CROP_X_OFFSET

 

RW - 0x0

RW - 0x00

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CROP_X_OFFSET

CROP_Y_SIZE

CROP_X_SIZE

RW - 0x00

RW - 0x00

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

24

CROP_ENABLE

Enable bit to crop

RW

-

-

0x0

23:18

CROP_Y_OFFSET

Y offset from 0,0 output picture to crop in Zone unit

RW

-

-

0x00

17:12

CROP_X_OFFSET

X offset from 0,0 output picture to crop in Zone unit

RW

-

-

0x00

11:6

CROP_Y_SIZE

Y size to crop in Zone unit

RW

-

-

0x00

5:0

CROP_X_SIZE

X size to crop in Zone unit

RW

-

-

0x00

6

 

Register: SBSE_RESERVED_n[7]

Description

 : SBSE_RESERVED_n register

Offset

 : [0x48 - 0x60]

Absolute Address

 : [0x04A8 - 0x04C0]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RW

-

-

0x0000 0000

6


Block: STANDBY_CONTEXT_SHORT

Description

 :

3

 

Register: BINNING

Description

 : BINNING register

Offset

 : 0x0

Absolute Address

 : 0x04C4

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x02

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

4:0

VALUE

LONG context binning factor

RW

-

-

0x02

6

 

Register: DSS_MODE

Description

 : DSS_MODE register

Offset

 : 0x1

Absolute Address

 : 0x04C5

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x02

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

LONG context DSS mode:

        0x00 DSS_DISABLE: DSS_DISABLE

        0x01 DSS_LONG: DSS_LONG

        0x02 DSS_SHORT: DSS_SHORT

RW

-

-

0x02

6

 

Register: REPEAT

Description

 : REPEAT register

Offset

 : 0x2

Absolute Address

 : 0x04C6

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Only in COMPOSITE mode, number of SHORT context repetition

RW

-

-

0x00

6

 

Register: SBCS_RESERVED

Description

 : SBCS_RESERVED register

Offset

 : 0x3

Absolute Address

 : 0x04C7

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

 

RW

-

-

0x00

6


Block: STANDBY_CONTEXT_LONG

Description

 :

3

 

Register: BINNING

Description

 : BINNING register

Offset

 : 0x0

Absolute Address

 : 0x04C8

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x02

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

4:0

VALUE

LONG context binning factor

RW

-

-

0x02

6

 

Register: DSS_MODE

Description

 : DSS_MODE register

Offset

 : 0x1

Absolute Address

 : 0x04C9

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x01

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

LONG context DSS mode:

        0x00 DSS_DISABLE: DSS_DISABLE

        0x01 DSS_LONG: DSS_LONG

        0x02 DSS_SHORT: DSS_SHORT

RW

-

-

0x01

6

 

Register: REPEAT

Description

 : REPEAT register

Offset

 : 0x2

Absolute Address

 : 0x04CA

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Only in COMPOSITE mode, number of LONG context repetition

RW

-

-

0x00

6

 

Register: SBCL_RESERVED

Description

 : SBCL_RESERVED register

Offset

 : 0x3

Absolute Address

 : 0x04CB

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

 

RW

-

-

0x00

6


Block: STREAM_CONTEXT_SHORT

Description

 :

3

 

Register: STEP_NUMBER

Description

 : STEP_NUMBER register

Offset

 : 0x0

Absolute Address

 : 0x04CC

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x7

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

3:0

VALUE

Number of measure steps (6 or 7)

RW

-

-

0x7

6

 

Register: VCSEL_CONFIG_CH0_STEP_n[8]

Description

 : VCSEL_CONFIG_CH0_STEP_n register

Offset

 : [0x1 - 0x8]

Absolute Address

 : [0x04CD - 0x04D4]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x20

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

Step laser driver configuration selection for channel 0

RW

-

-

0x20

6

 

Register: VCSEL_CONFIG_CH1_STEP_n[8]

Description

 : VCSEL_CONFIG_CH1_STEP_n register

Offset

 : [0x9 - 0x10]

Absolute Address

 : [0x04D5 - 0x04DC]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x20

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

Step laser driver configuration selection for channel 1

RW

-

-

0x20

6

 

Register: BLANKING_STEP_n[8]

Description

 : BLANKING_STEP_n register

Offset

 : [0x12 - 0x20]

Absolute Address

 : [0x04DE - 0x04EC]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

9:0

VALUE

Step blanking (ranging clock cycles)

RW

-

-

0x000

6

 

Register: MAX_DITHERING_STEP_n[8]

Description

 : MAX_DITHERING_STEP_n register

Offset

 : [0x22 - 0x29]

Absolute Address

 : [0x04EE - 0x04F5]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

4:0

VALUE

Step max dithering (ranging clock cycles)

RW

-

-

0x00

6

 

Register: PULSE_WIDTH_SHORT

Description

 : PULSE_WIDTH_SHORT register

Offset

 : 0x2A

Absolute Address

 : 0x04F6

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x15

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Laser Pulse Width for short window (used by DSS). Unit is 1/16ns (21 for 1.3ns)

RW

-

-

0x15

6

 

Register: PULSE_WIDTH_LONG

Description

 : PULSE_WIDTH_LONG register

Offset

 : 0x2B

Absolute Address

 : 0x04F7

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x15

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Laser Pulse Width for long window (used by DSS). Unit is 1/16ns (42 for 2.6ns)

RW

-

-

0x15

6

 

Register: DISTANCE_REF_LONG_OFFSET

Description

 : DISTANCE_REF_LONG_OFFSET register

Offset

 : 0x2C

Absolute Address

 : 0x04F8

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x60

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Distance offset for REF long distance computation signed from -64 to 63. No impact on pulse postion.

RW

-

-

0x60

6

 

Register: DISTANCE_RTN_LONG_OFFSET

Description

 : DISTANCE_RTN_LONG_OFFSET register

Offset

 : 0x2D

Absolute Address

 : 0x04F9

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Distance offset for RTN long distance computation signed from -64 to 63. No impact on pulse position.

RW

-

-

0x00

6

 

Register: DISTANCE_RTN_SHORT_OFFSET

Description

 : DISTANCE_RTN_SHORT_OFFSET register

Offset

 : 0x2E

Absolute Address

 : 0x04FA

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Distance offset for RTN short distance computation signed from -64 to 63. No impact on pulse postion.

RW

-

-

0x00

6

 

Register: DISTANCE_SWITCHOVER

Description

 : DISTANCE_SWITCHOVER register

Offset

 : 0x30

Absolute Address

 : 0x04FC

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0145

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Distance threshold for short/long distance final choice

RW

-

-

0x0145

6

 

Register: DST_SCL

Description

 : DST_SCL register

Offset

 : 0x32

Absolute Address

 : 0x04FE

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0257

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

DST_SCL value for CABDT

RW

-

-

0x0257

6

 

Register: NB_SHOT_STEP_n[8]

Description

 : NB_SHOT_STEP_n register

Offset

 : [0x34 - 0x50]

Absolute Address

 : [0x0500 - 0x051C]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

VALUE

 

RW - 0x00 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x00 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

23:0

VALUE

Step number of shot

RW

-

-

0x00 0000

6

 

Register: GROUP_HOLD

Description

 : GROUP_HOLD register

Offset

 : 0x54

Absolute Address

 : 0x0520

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

 

        0x00 HOLD_OFF: Page update complete

        0x01 HOLD_ON: Page update ongoing

RW

-

-

0x0

6

 

Register: SRCS_RESERVED_n[10]

Description

 : SRCS_RESERVED_n register

Offset

 : [0x58 - 0x7C]

Absolute Address

 : [0x0524 - 0x0548]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RW

-

-

0x0000 0000

6


Block: STREAM_CONTEXT_LONG

Description

 :

3

 

Register: STEP_NUMBER

Description

 : STEP_NUMBER register

Offset

 : 0x0

Absolute Address

 : 0x054C

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x6

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

3:0

VALUE

Number of measure steps (6 or 7)

RW

-

-

0x6

6

 

Register: VCSEL_CONFIG_CH0_STEP_n[8]

Description

 : VCSEL_CONFIG_CH0_STEP_n register

Offset

 : [0x1 - 0x8]

Absolute Address

 : [0x054D - 0x0554]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x20

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

Step laser driver configuration selection for channel 0

RW

-

-

0x20

6

 

Register: VCSEL_CONFIG_CH1_STEP_n[8]

Description

 : VCSEL_CONFIG_CH1_STEP_n register

Offset

 : [0x9 - 0x10]

Absolute Address

 : [0x0555 - 0x055C]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x20

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

Step laser driver configuration selection for channel 1

RW

-

-

0x20

6

 

Register: BLANKING_STEP_n[8]

Description

 : BLANKING_STEP_n register

Offset

 : [0x12 - 0x20]

Absolute Address

 : [0x055E - 0x056C]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

9:0

VALUE

Step blanking (ranging clock cycles)

RW

-

-

0x000

6

 

Register: MAX_DITHERING_STEP_n[8]

Description

 : MAX_DITHERING_STEP_n register

Offset

 : [0x22 - 0x29]

Absolute Address

 : [0x056E - 0x0575]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

4:0

VALUE

Step max dithering (ranging clock cycles)

RW

-

-

0x00

6

 

Register: PULSE_WIDTH_SHORT

Description

 : PULSE_WIDTH_SHORT register

Offset

 : 0x2A

Absolute Address

 : 0x0576

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x2A

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Laser Pulse Width for short window (used by DSS). Unit is 1/16ns (21 for 1.3ns)

RW

-

-

0x2A

6

 

Register: PULSE_WIDTH_LONG

Description

 : PULSE_WIDTH_LONG register

Offset

 : 0x2B

Absolute Address

 : 0x0577

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x2A

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Laser Pulse Width for long window (used by DSS). Unit is 1/16ns (42 for 2.6ns)

RW

-

-

0x2A

6

 

Register: DISTANCE_REF_LONG_OFFSET

Description

 : DISTANCE_REF_LONG_OFFSET register

Offset

 : 0x2C

Absolute Address

 : 0x0578

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x60

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Distance offset for REF long distance computation signed from -64 to 63. No impact on pulse postion.

RW

-

-

0x60

6

 

Register: DISTANCE_RTN_LONG_OFFSET

Description

 : DISTANCE_RTN_LONG_OFFSET register

Offset

 : 0x2D

Absolute Address

 : 0x0579

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Distance offset for RTN long distance computation signed from -64 to 63. No impact on pulse position.

RW

-

-

0x00

6

 

Register: DISTANCE_RTN_SHORT_OFFSET

Description

 : DISTANCE_RTN_SHORT_OFFSET register

Offset

 : 0x2E

Absolute Address

 : 0x057A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x02

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Distance offset for RTN short distance computation signed from -64 to 63. No impact on pulse postion.

RW

-

-

0x02

6

 

Register: DISTANCE_SWITCHOVER

Description

 : DISTANCE_SWITCHOVER register

Offset

 : 0x30

Absolute Address

 : 0x057C

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x028A

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Distance threshold for short/long distance final choice

RW

-

-

0x028A

6

 

Register: DST_SCL

Description

 : DST_SCL register

Offset

 : 0x32

Absolute Address

 : 0x057E

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0256

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

DST_SCL value for CABDT

RW

-

-

0x0256

6

 

Register: NB_SHOT_STEP_n[8]

Description

 : NB_SHOT_STEP_n register

Offset

 : [0x34 - 0x50]

Absolute Address

 : [0x0580 - 0x059C]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

VALUE

 

RW - 0x00 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x00 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

23:0

VALUE

Step number of shot

RW

-

-

0x00 0000

6

 

Register: GROUP_HOLD

Description

 : GROUP_HOLD register

Offset

 : 0x54

Absolute Address

 : 0x05A0

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

 

        0x00 HOLD_OFF: Page update complete

        0x01 HOLD_ON: Page update ongoing

RW

-

-

0x0

6

 

Register: SRCL_RESERVED_n[10]

Description

 : SRCL_RESERVED_n register

Offset

 : [0x58 - 0x7C]

Absolute Address

 : [0x05A4 - 0x05C8]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RW

-

-

0x0000 0000

6


Block: DEBUG_SETTINGS

Description

 :

3

 

Register: LDD_FW_BYPASS

Description

 : LDD_FW_BYPASS register

Offset

 : 0x8

Absolute Address

 : 0x05D4

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Disable accesses to Laser Driver during Streaming

RW

-

-

0x0

6

 

Register: INTENSITY_SPAD_SELECT

Description

 : INTENSITY_SPAD_SELECT register

Offset

 : 0x9

Absolute Address

 : 0x05D5

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x04

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

SPAD selection in intensity mode:

        0x00 SPAD_0: spad id 0 enabled only

        0x01 SPAD_1: spad id 1 enabled only

        0x02 SPAD_2: spad id 2 enabled only

        0x03 SPAD_3: spad id 3 enabled only

        0x04 AUTO: Automatic cycling from SPAD_0 to SPAD_3

RW

-

-

0x04

6

 

Register: DSS_DEFAULT_INIT_LUT

Description

 : DSS_DEFAULT_INIT_LUT register

Offset

 : 0xA

Absolute Address

 : 0x05D6

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x03

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

DEFAULT LUT index nb for DSS start

RW

-

-

0x03

6

 

Register: SHORT_DSS_OR_TREE_LIMIT

Description

 : SHORT_DSS_OR_TREE_LIMIT register

Offset

 : 0xC

Absolute Address

 : 0x05D8

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 01F4

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 01F4

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

or_tree_pk_rate_limit: typically 80e6.

In FP 656<= 80e6/121900

RW

-

-

0x0000 01F4

6

 

Register: SHORT_DSS_RATE_SWITCH_LO

Description

 : SHORT_DSS_RATE_SWITCH_LO register

Offset

 : 0x10

Absolute Address

 : 0x05DC

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

rate_switch low : typically 200e6.

in FP 1640<=200e6/121900

RW

-

-

0x0000 0000

6

 

Register: SHORT_DSS_RATE_SWITCH_HI

Description

 : SHORT_DSS_RATE_SWITCH_HI register

Offset

 : 0x14

Absolute Address

 : 0x05E0

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

rate_switch high: typically 200e6.

in FP 1640<=200e6/121900

RW

-

-

0x0000 0000

6

 

Register: SHORT_DSS_AMB_WEIGHT

Description

 : SHORT_DSS_AMB_WEIGHT register

Offset

 : 0x18

Absolute Address

 : 0x05E4

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x08

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

ambient_weight: typically 1.

 In FP 16<=1*16

RW

-

-

0x08

6

 

Register: SHORT_DSS_RATE_GAIN

Description

 : SHORT_DSS_RATE_GAIN register

Offset

 : 0x19

Absolute Address

 : 0x05E5

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x15

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

signal_rate_gain: typically 1.3. (In fixed point 21<= 1.3*16)

RW

-

-

0x15

6

 

Register: SHORT_DSS_COEF_n[10]

Description

 : SHORT_DSS_COEF_n register

Offset

 : [0x1A - 0x2C]

Absolute Address

 : [0x05E6 - 0x05F8]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

LUT index

RW

-

-

0x0000

6

 

Register: SHORT_DSS_INDEX_NB

Description

 : SHORT_DSS_INDEX_NB register

Offset

 : 0x2E

Absolute Address

 : 0x05FA

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x07

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Nb of LUT indexes (7, 8, 9 or 10)

RW

-

-

0x07

6

 

Register: SHORT_DSS_LUT_n[40]

Description

 : SHORT_DSS_LUT_n register

Offset

 : [0x2F - 0x56]

Absolute Address

 : [0x05FB - 0x0622]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

LUT pattern (2*2 pixel => 16 spads). Boolean bits : 3 2 1 0. The 4 MSB are not used

RW

-

-

0x00

6

 

Register: SHORT_DSS_EFF_SPAD_n[10]

Description

 : SHORT_DSS_EFF_SPAD_n register

Offset

 : [0x58 - 0x6A]

Absolute Address

 : [0x0624 - 0x0636]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

effective SPAD value per LUT used for internal DSS computation

RW

-

-

0x0000

6

 

Register: DBSE_RESERVED0_n[30]

Description

 : DBSE_RESERVED0_n register

Offset

 : [0x6C - 0x89]

Absolute Address

 : [0x0638 - 0x0655]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED area

RW

-

-

0x00

6

 

Register: LONG_DSS_OR_TREE_LIMIT

Description

 : LONG_DSS_OR_TREE_LIMIT register

Offset

 : 0x8C

Absolute Address

 : 0x0658

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 01F4

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 01F4

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

or_tree_pk_rate_limit: typically 80e6.

In FP 656<= 80e6/121900

RW

-

-

0x0000 01F4

6

 

Register: LONG_DSS_RATE_SWITCH_LO

Description

 : LONG_DSS_RATE_SWITCH_LO register

Offset

 : 0x90

Absolute Address

 : 0x065C

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

rate_switch low: typically 200e6.

in FP 1640<=200e6/121900

RW

-

-

0x0000 0000

6

 

Register: LONG_DSS_RATE_SWITCH_HI

Description

 : LONG_DSS_RATE_SWITCH_HI register

Offset

 : 0x94

Absolute Address

 : 0x0660

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

rate_switch high: typically 200e6.

in FP 1640<=200e6/121900

RW

-

-

0x0000 0000

6

 

Register: LONG_DSS_AMB_WEIGHT

Description

 : LONG_DSS_AMB_WEIGHT register

Offset

 : 0x98

Absolute Address

 : 0x0664

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x08

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

ambient_weight: typically 1.

 In FP 16<=1*16

RW

-

-

0x08

6

 

Register: LONG_DSS_RATE_GAIN

Description

 : LONG_DSS_RATE_GAIN register

Offset

 : 0x99

Absolute Address

 : 0x0665

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x15

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

signal_rate_gain: typically 1.3. (In fixed point 21<= 1.3*16)

RW

-

-

0x15

6

 

Register: LONG_DSS_COEF_n[10]

Description

 : LONG_DSS_COEF_n register

Offset

 : [0x9A - 0xAC]

Absolute Address

 : [0x0666 - 0x0678]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

LUT index

RW

-

-

0x0000

6

 

Register: LONG_DSS_INDEX_NB

Description

 : LONG_DSS_INDEX_NB register

Offset

 : 0xAE

Absolute Address

 : 0x067A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x07

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Nb of LUT indexes (7, 8, 9 or 10)

RW

-

-

0x07

6

 

Register: LONG_DSS_LUT_n[40]

Description

 : LONG_DSS_LUT_n register

Offset

 : [0xAF - 0xD6]

Absolute Address

 : [0x067B - 0x06A2]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

LUT pattern (2*2 pixel => 16 spads). Boolean bits : 3 2 1 0. The 4 MSB are not used

RW

-

-

0x00

6

 

Register: LONG_DSS_EFF_SPAD_n[10]

Description

 : LONG_DSS_EFF_SPAD_n register

Offset

 : [0xD8 - 0xEA]

Absolute Address

 : [0x06A4 - 0x06B6]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

effective SPAD value per LUT used for internal DSS computation

RW

-

-

0x0000

6

 

Register: DBSE_RESERVED1_n[29]

Description

 : DBSE_RESERVED1_n register

Offset

 : [0xEC - 0x108]

Absolute Address

 : [0x06B8 - 0x06D4]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED area

RW

-

-

0x00

6

 

Register: CALIBRATION_DISABLE

Description

 : CALIBRATION_DISABLE register

Offset

 : 0x109

Absolute Address

 : 0x06D5

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Disable Calibration Phase at start of stream

RW

-

-

0x0

6

 

Register: LINEAR_COMPENS_CH1

Description

 : LINEAR_COMPENS_CH1 register

Offset

 : 0x10A

Absolute Address

 : 0x06D6

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x02

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Linear compensation LDD offset added to step5 and 6 channel 1. (signed value in quarter of bin)

RW

-

-

0x02

6

 

Register: LINEAR_COMPENS_CH2

Description

 : LINEAR_COMPENS_CH2 register

Offset

 : 0x10B

Absolute Address

 : 0x06D7

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x02

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Linear compensation LDD offset added to step5 and 6 channel 2. (signed value in quarter of bin)

RW

-

-

0x02

6

 

Register: DBSE_RESERVED2_n[4]

Description

 : DBSE_RESERVED2_n register

Offset

 : [0x10C - 0x118]

Absolute Address

 : [0x06D8 - 0x06E4]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

RESERVED

RW

-

-

0x0000 0000

6


Block: OTP_MIRROR

Description

 :

3

 

Register: NVM_MODULE_ID

Description

 : NVM_MODULE_ID register

Offset

 : 0x0

Absolute Address

 : 0x06E8

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

Identifiers

RW

-

-

0x0000 0000

6

 

Register: GLOBAL_DISTANCE_OFFSET

Description

 : GLOBAL_DISTANCE_OFFSET register

Offset

 : 0x4

Absolute Address

 : 0x06EC

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Global distance offset on 16LSB

RW

-

-

0x0000

6

 

Register: OTP1_RESERVED0

Description

 : OTP1_RESERVED0 register

Offset

 : 0x6

Absolute Address

 : 0x06EE

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

RESERVED

RW

-

-

0x0000

6

 

Register: DISTANCE_OFFSET_0_n[945]

Description

 : DISTANCE_OFFSET_0_n register

Offset

 : [0x8 - 0x3B8]

Absolute Address

 : [0x06F0 - 0x0AA0]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Per pixel distance relative offset map.

(6bits signed )

RW

-

-

0x00

6

 

Register: OTP1_RESERVED1_n[15]

Description

 : OTP1_RESERVED1_n register

Offset

 : [0x3B9 - 0x3C7]

Absolute Address

 : [0x0AA1 - 0x0AAF]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: DSS_LUT_n[40]

Description

 : DSS_LUT_n register

Offset

 : [0x3C8 - 0x3EF]

Absolute Address

 : [0x0AB0 - 0x0AD7]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

DSS LUT with a maximum of 10 indexes (8 by default)

1 byte per MPIX of the 2x2 aperture pattern

RW

-

-

0x00

6

 

Register: OTP1_RESERVED2_n[8]

Description

 : OTP1_RESERVED2_n register

Offset

 : [0x3F0 - 0x3F7]

Absolute Address

 : [0x0AD8 - 0x0ADF]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: DEFECT_SPAD_n[20]

Description

 : DEFECT_SPAD_n register

Offset

 : [0x3F8 - 0x41E]

Absolute Address

 : [0x0AE0 - 0x0B06]

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DEFECT_X

DEFECT_Y

DEFECT_SPAD_NB

RW - 0x00

RW - 0x00

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:9

DEFECT_X

32 bits per index (1 byte per MPIX of the 2x2 aperture pattern)

RW

-

-

0x00

8:2

DEFECT_Y

Y coordonate

RW

-

-

0x00

1:0

DEFECT_SPAD_NB

Spad number

RW

-

-

0x0

6

 

Register: OPTICAL_OFFSET_X

Description

 : OPTICAL_OFFSET_X register

Offset

 : 0x420

Absolute Address

 : 0x0B08

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

X offset of the optical center

RW

-

-

0x0

6

 

Register: OPTICAL_OFFSET_Y

Description

 : OPTICAL_OFFSET_Y register

Offset

 : 0x421

Absolute Address

 : 0x0B09

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

1:0

VALUE

Y offset of the optical center

RW

-

-

0x0

6

 

Register: RESIDUAL_OFFSET_X

Description

 : RESIDUAL_OFFSET_X register

Offset

 : 0x422

Absolute Address

 : 0x0B0A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

X residual offset between what is programmed and real optical center (S2.1 in SPAD unit-> step of 0.5)

RW

-

-

0x00

6

 

Register: RESIDUAL_OFFSET_Y

Description

 : RESIDUAL_OFFSET_Y register

Offset

 : 0x423

Absolute Address

 : 0x0B0B

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Y Residual offset between what is programmed and real optical center (S2.1 in SPAD unit-> step of 0.5)

RW

-

-

0x00

6

 

Register: CAL_TEMP_DEGC

Description

 : CAL_TEMP_DEGC register

Offset

 : 0x424

Absolute Address

 : 0x0B0C

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

Measured temperature during calibration for tracability (in °C)

RW

-

-

0x00

6

 

Register: TEMP_SENSOR_VALUE

Description

 : TEMP_SENSOR_VALUE register

Offset

 : 0x425

Absolute Address

 : 0x0B0D

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

4:0

VALUE

Thermal sensor correction value (to copy in DCORRECT)

RW

-

-

0x00

6

 

Register: OTP1_RESERVED3_n[2]

Description

 : OTP1_RESERVED3_n register

Offset

 : [0x426 - 0x427]

Absolute Address

 : [0x0B0E - 0x0B0F]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: AUTO_VHV_TRIM_VOLTAGE

Description

 : AUTO_VHV_TRIM_VOLTAGE register

Offset

 : 0x428

Absolute Address

 : 0x0B10

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

9:0

VALUE

AUTO VHV found voltage at 60°C at EWS (in U5.5 V)

RW

-

-

0x000

6

 

Register: AUTO_VHV_TRIM_TEMP

Description

 : AUTO_VHV_TRIM_TEMP register

Offset

 : 0x42A

Absolute Address

 : 0x0B12

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Temperature sensor reading (in °C) during AUTO VHV at EWS

RW

-

-

0x00

6

 

Register: BG_TRIM_IBIAS

Description

 : BG_TRIM_IBIAS register

Offset

 : 0x42C

Absolute Address

 : 0x0B14

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

BG IBias trimming (in S5.0)

RW

-

-

0x00

6

 

Register: BG_TRIM_VREF

Description

 : BG_TRIM_VREF register

Offset

 : 0x42D

Absolute Address

 : 0x0B15

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

5:0

VALUE

BG VRef trimming (in S5.0)

RW

-

-

0x00

6

 

Register: TEMP_TO_DAC_GAIN

Description

 : TEMP_TO_DAC_GAIN register

Offset

 : 0x42E

Absolute Address

 : 0x0B16

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Temperature to DAC setting gain (Q8.8)

RW

-

-

0x0000

6

 

Register: AUTO_VHV_IDAC_SEL_FMT

Description

 : AUTO_VHV_IDAC_SEL_FMT register

Offset

 : 0x430

Absolute Address

 : 0x0B18

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

AUTO VHV found HV BOOST DAC Setting at FMT

RW

-

-

0x00

6

 

Register: AUTO_VHV_TEMP_FMT

Description

 : AUTO_VHV_TEMP_FMT register

Offset

 : 0x431

Absolute Address

 : 0x0B19

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Temperature sensor reading (in °C) during AUTO VHV at FMT

RW

-

-

0x00

6

 

Register: OTP1_RESERVED4

Description

 : OTP1_RESERVED4 register

Offset

 : 0x432

Absolute Address

 : 0x0B1A

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: TEMP_TO_DAC_OFFSET

Description

 : TEMP_TO_DAC_OFFSET register

Offset

 : 0x433

Absolute Address

 : 0x0B1B

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Temperature to DAC setting offset (S8)

RW

-

-

0x00

6

 

Register: REF_ARRAY_CHECK

Description

 : REF_ARRAY_CHECK register

Offset

 : 0x434

Absolute Address

 : 0x0B1C

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

“Reference array check” lower threshold for checking reference array counts do not go below this threshold (in number of events)

RW

-

-

0x0000 0000

6

 

Register: REF_ARRAY_SPAD_EN

Description

 : REF_ARRAY_SPAD_EN register

Offset

 : 0x438

Absolute Address

 : 0x0B20

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

VALUE

 

RW - 0x00 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x00 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

23:0

VALUE

Reference array SPAD enables (1 bit per SPAD)

RW

-

-

0x00 0000

6

 

Register: RAD2PERP_FOV_GAIN

Description

 : RAD2PERP_FOV_GAIN register

Offset

 : 0x43C

Absolute Address

 : 0x0B24

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Rad2Perp field of vue gain (U1.7)

RW

-

-

0x00

6

 

Register: OTP1_RESERVED5_n[3]

Description

 : OTP1_RESERVED5_n register

Offset

 : [0x43D - 0x43F]

Absolute Address

 : [0x0B25 - 0x0B27]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: DISTANCE_OFFSET_30_n[315]

Description

 : DISTANCE_OFFSET_30_n register

Offset

 : [0x440 - 0x57A]

Absolute Address

 : [0x0B28 - 0x0C62]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Per pixel distance relative offset map.

(6bits signed )

RW

-

-

0x00

6

 

Register: OTP1_RESERVED6_n[29]

Description

 : OTP1_RESERVED6_n register

Offset

 : [0x57B - 0x597]

Absolute Address

 : [0x0C63 - 0x0C7F]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: CAL_AMP_COEFF_n[35]

Description

 : CAL_AMP_COEFF_n register

Offset

 : [0x598 - 0x5BA]

Absolute Address

 : [0x0C80 - 0x0CA2]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

7x5 Amplitude coefficient grid captured at FMT DMAX

from 0x0 (bottom left), 0x1,0x2… to …4x4,4x5,4x6

8bits unsigned

RW

-

-

0x00

6

 

Register: CAL_AMP_SCALER

Description

 : CAL_AMP_SCALER register

Offset

 : 0x5BB

Absolute Address

 : 0x0CA3

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

scaler to encode full amplitude

8 bits unsigned

RW

-

-

0x00

6

 

Register: CAL_AMP_DISTANCE

Description

 : CAL_AMP_DISTANCE register

Offset

 : 0x5BC

Absolute Address

 : 0x0CA4

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

distance in mm at which amplitude calibration was captured

16bits unsigned

RW

-

-

0x0000

6

 

Register: CAL_AMP_EXPO

Description

 : CAL_AMP_EXPO register

Offset

 : 0x5BE

Absolute Address

 : 0x0CA6

Addressing Mode

 : 32-bits

4

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

15:0

VALUE

Exposure number in final step in FMT use Case

RW

-

-

0x0000

6

 

Register: CAL_AMP_REFLECTANCE

Description

 : CAL_AMP_REFLECTANCE register

Offset

 : 0x5C0

Absolute Address

 : 0x0CA8

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

reflectance in % in which amplitude calibration was captured

8bits unsigned

RW

-

-

0x00

6

 

Register: OTP1_RESERVED7_n[11]

Description

 : OTP1_RESERVED7_n register

Offset

 : [0x5C1 - 0x5CB]

Absolute Address

 : [0x0CA9 - 0x0CB3]

Addressing Mode

 : 32-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: TEST_ENGI_DATA_n[13]

Description

 : TEST_ENGI_DATA_n register

Offset

 : [0x5CC - 0x5FC]

Absolute Address

 : [0x0CB4 - 0x0CE4]

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VALUE

RW - 0x0000 0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VALUE

RW - 0x0000 0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:0

VALUE

 

RW

-

-

0x0000 0000

6


Block: CUSTOM_OTP_MIRROR

Description

 :

3

 

Register: I2C_SLAVE_ID

Description

 : I2C_SLAVE_ID register

Offset

 : 0x0

Absolute Address

 : 0x0CE8

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

6:0

VALUE

I2C Slave address

RW

-

-

0x00

6

 

Register: COTP_RESERVED0_n[3]

Description

 : COTP_RESERVED0_n register

Offset

 : [0x1 - 0x3]

Absolute Address

 : [0x0CE9 - 0x0CEB]

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6

 

Register: I3C_INSTANCE_ID

Description

 : I3C_INSTANCE_ID register

Offset

 : 0x4

Absolute Address

 : 0x0CEC

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

 

VALUE

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

3:0

VALUE

I3C PID

RW

-

-

0x0

6

 

Register: COTP_RESERVED1_n[43]

Description

 : COTP_RESERVED1_n register

Offset

 : [0x5 - 0x2F]

Absolute Address

 : [0x0CED - 0x0D17]

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6


Block: OTP_MIRROR_SECTION2

Description

 :

3

 

Register: DISTANCE_OFFSET_40_n[441]

Description

 : DISTANCE_OFFSET_40_n register

Offset

 : [0x0 - 0x1B8]

Absolute Address

 : [0x0D18 - 0x0ED0]

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

Per pixel distance relative offset map.

(6bits signed )

RW

-

-

0x00

6

 

Register: OTP2_RESERVED0_n[23]

Description

 : OTP2_RESERVED0_n register

Offset

 : [0x1B9 - 0x1CF]

Absolute Address

 : [0x0ED1 - 0x0EE7]

Addressing Mode

 : 8-bits

4

 

7

6

5

4

3

2

1

0

VALUE

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

7:0

VALUE

RESERVED

RW

-

-

0x00

6


Block: SOC_I3C

Description

 : I3CSLAVELITE register bank

3

 

Register: SOC_I3C_DEVICEID

Description

 : DeviceID Control register

Offset

 : 0x8

Absolute Address

 : 0xD208

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

HW_STATIC_ADDR

 

ID_CHANGE_CTRL

 

RO - 0x29

 

RW - 0x0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

STATIC_ADDR_EN

 

DEVICEID

 

RW - 0x1

 

RW - 0x00

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

30:24

HW_STATIC_ADDR

default hardware static address. This value is provided to the IP thru i_external_device_addr input bus

RO

-

-

0x29

16

ID_CHANGE_CTRL

 

        0x0 FALSE: Static address of I3C core is controlled by hardware pins

        0x1 TRUE: Static address of I3C core is controlled by firmware register

RW

-

-

0x0

8

STATIC_ADDR_EN

 

        0x0 FALSE: I3C slave will not have a static address

        0x1 TRUE: I3C or I2C slave will use as static address the value selected by id_change_ctrl

RW

-

-

0x1

6:0

DEVICEID

static device address of the I2C or I3C slave

RW

-

-

0x00

6

 

Register: SOC_I3C_PID_INST_ID

Description

 : Instance ID value of device PID

Offset

 : 0x38

Absolute Address

 : 0xD238

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

PID_INST_ID

 

RW - 0x0

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

3:0

PID_INST_ID

Bits 15 to 12 of the PID vector. Identifies the individual device using a method selected by the system designer. See MIPI I3C spec for details

RW

-

-

0x0

6


Block: SOC_CABDT

Description

 :

3

 

Register: SOC_CABDT_ALGO_SCALE

Description

 : ALGO_SCALE register

Offset

 : 0x20

Absolute Address

 : 0xD520

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

amb_att

 

 

RW - 0x0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

27:24

amb_att

ambient attenuation (2^val : 1,2,4,8,16, 32)

RW

-

-

0x0

6

 

Register: SOC_CABDT_DIST_SCALE

Description

 : DIST_SCALE register

Offset

 : 0x24

Absolute Address

 : 0xD524

Addressing Mode

 : 32-bits

4

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

short_scl

RW - 0x0000

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

long_scl

RW - 0x0000

5

 

Bit

Name

Description

SW Access

HW Access

Protection

Reset

31:16

short_scl

short amplitude scaling for short/long distance final choice

RW

-

-

0x0000

15:0

long_scl

long amplitude scaling for short/long distance final choice

RW

-

-

0x0000

6


Access policy

Access policy

Description

Effect of a Write on Current Field Value

Effect of a Read on Current Field Value

RO

  Read Only

  No effect.

  No effect.

RW

  Read Write

  Changed to written value.

  No effect.

7