SNUG World 2021
DATE: 20-22 April – Virtual event
Synopsys is a key resource for ST, and we’ve got a lot to share in 8 papers covering our latest innovations in chip design at the virtual SNUGWorld 2021.
Check out the agenda to find us!
|April 20||10:25am||Small Range Hold Fixing with LoadCap Cell in Primetime||Anuradha Ray
|April 21||10:00am||Efficient Post-Layout Simulation and EMIR Validation with StarRC GPD Flow||Atul Bhargava|
|April 21||11:25am||How to achieve the best PPA on an ultra-low power STM32 microcontroller: SAIF driven synthesis flow||Nathalie MELOUX|
|April 21||10:00am||Using PrimeShield variation analysis to create a more robust core at fractionn of the cost of flat margin||Sebastien Marchal|
|Ensuring Functional Safety of Memory IP Using TestMAX CustomFault™||Kedar Janardan Dhori|
|April 22||10:00am||STMicroelectronics Memory Verification Flow Optimization Using Synopsys AMS Solutions||Jean-Christophe Lafont|
|April 22||10:25am||Decrypting Paradox of Timing Issues with Tweaker||Apoorv Garg
|April 22||11:00am||Wafer Sort Parameters Post Processing for Assembly Inkless Map Generation||Sebastien Desmaison|
Not only ST presents different innovations at the Conference, but it is also present in the Technical Committee:
Tarun Chawla Giuseppe Notarangelo
Stella Matarrese Alessandro Valerio