IEDM 2022

IEDM 2022 – 68th International Electron Devices Meeting


DATE: 3-7 December, 2022
Hilton San Francisco Union Square – San Francisco, California
Type of conference: In-person with on-demand content available


Conference website

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Join ST at IEDM 2022 dedicated to the “75th anniversary of the transistor and the next transformative devices to address global challenges”.

The breakthroughs described at IEDM every year since it first started, only few years after the transistor was invented, push transistor and related technologies forward, enabling the ongoing digital transformation of society.

This year's conference includes over 220 technical presentations in addition to numerous educational opportunities, award presentations and other events highlighting the industry’s best work.

ST's experts will be present to share insights and talk about innovations in the areas of HR SiGe BiCMOS, FDSOI devices and image sensors.

date Time (PST) Title ST Speakers
Dec.6 9:00am Session 11: Advanced Devices for High RF and THz Applications Pascal Chevalier, co-Chair
Dec.6 12:00pm Session 11: Advanced Devices for High RF and THz Applications
Paper n.11.7

0.13 µm HR SiGe BiCMOS Technology exhibiting 169 fs Ron x Coff Switch Performance targeting WiFi 6E Fully Integrated RF Front-End-IC Solutions
What is this paper about?
In this paper, we review the optimization of an HR SiGe BiCMOS technology. State of the art RF switch performances have been achieved with RON × COFF of 169 fs and WiFi SPDT exhibiting insertion loss of ~0.8 dB @ 5.5 GHz and power handling capability exceeding 31 dBm.
Frederic Gianesello, speaker
Dec.7 9:30am Session 27: CMOs Scaling and PlatformsPaper n. 27.2
18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs
What is this paper about?
We report for the first time multiple FDSOI device innovations which have been implemented in the 18nm technology platform. 4 mixable Vts, high performance at low voltage (+80% wrt 28nm FDSOI at Vdd=0.6V) and low retention leakage (0.6pA at Vdd=0.55V) in high density SRAM bitcells have been demonstrated.
Olivier Weber, speaker
Dec.7 3:15pm Session 37: ODI - Silicon Image Sensors and Photonics
Paper n. 37.4:
 Tier BSI CIS with 3-Tier BSI CIS with 3D Sequential & Hybrid Bonding Enabling a 1.4um pitch, 106dB HDR Flicker Free Pixel
What is this paper about?

A 3-tier CIS combining 3D Sequential Integration for the 2-tier pixel realization & Hybrid Bonding for the logic circuitry connection is demonstrated. Thin film pixel transistors are built above photo-gate without congestion. Dual carrier collection 3DSI pixel offers an attractive dynamic range (106dB, Single Exposure) versus pixel pitch (1,4µm) trade-off
Francois Guyader, speaker
Dec.7 4:05pm Session 34: ALT - Advanced CMOS: Technology and Devices
Paper n.34.6 (invited)
FDSOI for cryo CMOS electronics: device characterization towards compact model
Whatis this paper about?

We present a status of FDSOI transistors electrical characterization for very low temperature operation. We highlight in particular singular transport and thermal effects occurring at low T. We also present the physical and analytical models associated with various characteristic electrical parameters, paving the way towards cryogenic compact models.
A. Juge, P. Galy, co-authors

ST is also part of the “Microwave, Millimeter Wave and Analog Technology” Committee with Pascal Chevalier