SNUG World 2021
DATE: 20-22 April – Virtual event
Synopsys is a key resource for ST, and we’ve got a lot to share in 8 papers covering our latest innovations in chip design at the virtual SNUGWorld 2021.
Check out the agenda to find us!
|Small Range Hold Fixing with LoadCap Cell in Primetime
|Efficient Post-Layout Simulation and EMIR Validation with StarRC GPD Flow
|How to achieve the best PPA on an ultra-low power STM32 microcontroller: SAIF driven synthesis flow
|Using PrimeShield variation analysis to create a more robust core at fractionn of the cost of flat margin
|Ensuring Functional Safety of Memory IP Using TestMAX CustomFault™
|Kedar Janardan Dhori
|STMicroelectronics Memory Verification Flow Optimization Using Synopsys AMS Solutions
|Decrypting Paradox of Timing Issues with Tweaker
|Wafer Sort Parameters Post Processing for Assembly Inkless Map Generation
Not only ST presents different innovations at the Conference, but it is also present in the Technical Committee:
Tarun Chawla Giuseppe Notarangelo
Stella Matarrese Alessandro Valerio