The 34th International Conference On VLSI Design & The 20th International Conference On Embedded Systems (VLSID 2021)
 | The 34th International Conference On VLSI Design & |
STMicroelectronics is Gold Sponsor of the 34th International Conference on VLSI Design (VLSID 2021), a global event held annually in India on VLSI design. It brings together all eco system stakeholders in the field of hardware and software system design, verification, test, EDA tools, and manufacturing of electronic systems.
2021 theme for VLSID 2021 is “From the transistor to cyber-physical systems, for solving societal challenges” and aims at emphasizing the potential of the VLSI community to find multidisciplinary solutions for the societal and engineering challenges of our times.
With several experts in the Committees, ST will be at the conference with a lot of contents, join the conversation with our experts!
| Date | Time (IST) | Title | Speakers |
| 22 Feb | 10:50am | Paper Presentation (session 1A) Negative Voltage Generator and Current DAC Based Regulator for Flash Memory | Vivek Tyagi Vikas Rana Shivam Kalla |
| 23 Feb | 8:00am | Paper presentation (session 3A) Adaptive Forward Body Bias Voltage Generator | Vivek Tyagi Vikas Rana |
| 23 Feb | 10:45am | Paper presentation Automated Generation of Current Controlled Oscillator (CCO) Layout using Template Reuse Flow | Rajeev Singh Vijay Singh Khati Akshita Bansal Aneesh R. Shastry (Cadence Design Systems) Vishesh Kumar (Cadence Design Systems) |
| 23 Feb | 10:45am | Paper presentation Early Layout Area and PLS Estimation by Designers | Akshita Mishra Sopaan Shukla |
| 23 Feb | 10:45am | Paper presentation (UDT-3) DPA(Design Planning and Analysis), a methodology to plan hierarchical design with congestion analysis to implement an automotive IP | Priya Meharde Priyanshi Shukla (Cadence Design Systems) |
| 23 Feb | 2:00pm | Keynote Cyber-Physical Systems for Industry 4.0: an industrial perspective | Philippe Magarshack |
| 24 Feb | 8:00am | Paper presentation (UDT-5) Methodology for Efficient SoC Constraint Modelling to Ensure Zero Hold Time of I2C Interface | Sanyam Grover Saurabh Srivastava |
| 24 Feb | 8:00am | Paper Presentation (UDT-7) High Performance High Density 6T SRAM Using Dynamically Enhanced Word-Line Drive | Dipti Arya Ashish Kumar |
User/Designer Track Committee
Chair Atul Bhargava, Alok Mittal, Deepti Miyan, Raunaque Quaiser
Sponsorship Co-Chair
Ashish Kumar