The X-CUBE-PERF-H7 Expansion Package aims to demonstrate the performance of the STM32H74x and STM32H75x architecture with its Arm® Cortex®‑M7 single core able to run at up to 480 MHz. The core instruction and data caches unleash its performance with 0-wait-state-like execution from different memories. The memories can be either internal or external, scattered across different domains (D1, D2, and D3), and accessed by the core through the TCM buses or the AXIM bus.
The Expansion Package is provided with several project configurations for the STM32H743I-EVAL Evaluation board. Each project allows the execution of application code and data storage in different memory locations such as internal memories as well as external memories located in different domains (D1, D2, and D3). Firmware results demonstrate that performance is similar when the code execution or data storage uses internal or external memories located in different domains. An FFT use case (provided by the CMSIS library) is proposed as an example with several toolchains: Keil® (MDK-ARM), IAR Systems® (EWARM), and STMicroelectronics System Workbench (SW4STM32). It can be ported easily to any other toolchain and any STM32H7 Series single-core device.
The generic microcontroller names STM32H74x and STM32H75x represent the STM32H7 Series single-core devices in the following product lines: STM32H742, STM32H743/753, and STM32H750 Value line.
- STM32H74x and STM32H75x performance demonstrator
- Code execution and data storage in different memory locations
- Arm® Cortex®‑M7
- Instruction cache (ICACHE)
- Data cache (DCACHE)
- D1, D2, and D3 power domains
- AXI and AHB bus matrices