Date: 7-9 September – Grenoble Minatec (hybrid format)
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ESSCIRC - ESSDERC is the annual European forum that brings together the scientific community to discuss recent advances in solid-state devices and circuits. Keynotes, paper presentations, joint sessions, workshops, and tutorials will cover all aspects of advanced devices and circuits. The 2021 edition is co-organized by CEA-Leti, STMicroelectronics, Soitec and Grenoble-Alpes University.

STMicroelectronics confirmed its Diamond sponsorship for the 2021 edition and we are contributing with multiple authoritative research papers, and are members of the Organizing Committee and the Technical Program Committee. The opening keynote of the conference, dedicated to AI @ the Edge, will be delivered by Joel Hartmann, ST’s Executive Vice President Digital & Smart Power Technology and Digital Front-End Manufacturing.

This year’s edition will be held in a hybrid format, with a mix of virtual and in-person sessions in Grenoble. Save the date and join us in September!

date Time (CET) Title Speakers
7 Sept 9:20 Joint Plenary – Keynote (A1L-1)
Artificial Intelligence: Why Moving it to the Edge?
Joel Hartmann, ST Presenter
7 Sept 10:30 Paper presentation (A2L-1)
Imaging Arrays & Detectors Session
4.6μm Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera
Cedric Tubert,  ST paper presenter
7 Sept 11:20 Paper Presentation (A2L-1)
Imaging Arrays & Detectors Session
Dark Count Rate in Single-Photon Avalanche Diode: Characterization and Modeling Study
Mathieu Sicre, ST paper presenter
7 Sept 14:30 Paper presentation (A4L-4)
Harvesting & Control Session
An 800-Ma Time-Based Boost Converter in 0.18um BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency
Alessandro Bertolini
Alessandro Gasparini, ST co-authors
7 Sept 17:45 Paper presentation (A5L-3)
High Performance Computing & Monitoring Session
A Review of Circuit Monitoring in 28nm FDSOI and 40nm Bulk CMOS Technologies
Sylvain Clerc,  ST paper presenter
8 Sept 11:45 Paper presentation (B2L-5)
Advanced Devices & Processing Session
Improving Ge-Rich GST ePCM Reliability Through BEOL Engineering
Andrea Redaelli, ST paper presenter
8 Sept 14:30 Paper presentation (B4L-5)
Simulation & Modeling of Defects & Traps Session
Impact of Hot Carrier Degradation on the Performances of Current Mirrors Based on a 55 nm BiCMOS Integrated Circuit Technology
Didier Céli, ST co-author
8 Sept 14:30 Paper presentation from SSC-L Special Edition ESSCIRC 2020(B4L-4)
Frequency Synthesis & Related Circuits
A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI
Andreia Cathelin, ST co-author
8 Sept 17:20 Paper Presentation (B5L-5)
Simulation & Modeling for Memory & Imaging Applications Session
Semi-Empirical Model for Optical Properties of SiGe Alloys Accounting for Strain and Temperature
Jeremy Grebot, ST paper presenter
8 Sept 17:45 Paper Presentation (B5L-5)
Simulation & Modeling for Memory & Imaging Applications Session
Comprehensive Modeling and Characterization of Photon Detection Efficiency and Jitter in Advanced SPAD Devices
Remi Helleboid, ST paper presenter
8 Sept 16:55 Paper Presentation (B5L-6)
Emerging Sensor Technologies Session
Design and Fabrication of a Ring-Coupled Mach-Zehnder Interferometer Gyroscope
Eva Kempf, ST paper presenter
9 Sept 14:30 Paper Presentation (C4L-3)
High-speed Data Converters Session
200-GS/S ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator
Pascal Chevalier, Andreia Cathelin,
ST co-authors
9 Sept 14:30 Paper presentation from SSC-L Special Edition ESSCIRC 2020(C4L-4)
Digital Design Solutions for Wireless Communications
A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS
Angel de Dios Gonzalez
ST paper presenter





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