The ST54J_CLF includes near-field communication (NFC) functions in the three operating modes: Card Emulation, Reader/Writer and Peer-to-Peer communication. It is based on an advanced Arm Cortex-M3 32-bit microcontroller running at 56 MHz.
The ST54J_CLF is best in class in terms of RF output power (up to 2 W). Thanks to improved low-power card detection, when operating in Reader/Writer mode, the ST54J_CLF is capable, in low-power mode, of detecting the presence of a card/tag from a distance greater than the Reader mode performance.
When operating in Card Emulation mode, the ST54J_CLF is capable of operating without an external quartz or an external reference clock source, contributing to further reducing the current consumption of the system in low-power mode.
The ST54J_CLF features two external master SWP interfaces and controls the embedded SE (ST54J_SE) with an internal SWP interface. Thanks to an enhanced power switch system, the CLF manages its own power supply and that of the associated secure elements (ST54J_SE, UICC_1 and UICC_2). It supports NCI 2.0.
The ST54J_SE features an Arm SecurCore SC300™ 32-bit RISC core cadenced at 100 MHz. This core is built on the Cortex-M3 core, with additional security features to help to protect against advanced forms of attack. Strong, multiple-fault protection mechanisms covering the CPU, memories and buses ensure high fault detection, thus facilitating the development of highly secure software. The ST54J_SE offers a serial communication interface fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1) and an internal single-wire protocol (SWP) interface for communication with the ST54J_CLF. The ST54J_SE features hardware accelerators for advanced cryptographic functions. The EDES peripheral provides a secure DES (Data Encryption Standard) algorithm implementation, while the NESCRYPT cryptoprocessor efficiently supports the public key algorithm. The AES peripheral ensures secure and fast AES algorithm implementation. A comprehensive range of power-saving modes enables the design of efficient low-power applications.
The ST54J includes an HS-UART (high-speed universal asynchronous receiver/transmitter) interface that operates at up to 8 Mbit/s. It also boasts SPI and I²C Master/Slave interfaces, which are shared between the ST54J_CLF and the ST54J_SE.
Data transfer between the ST54J_CLF and the ST54J_SE is optimized by the use of an internal shared memory and the IPC interface that operates at up to 120 Mbits/s.
The MIFARE R/W mode feature availability depends on the license conditions. Please contact your local ST representative for further information.
The ST54J is manufactured in an ECOPACK®-compliant, 3.5 × 3.5 × 0.41 mm, 81-ball wafer-level chip-scale package (WLCSP). The WLCSP offers a more compact footprint, while minimizing die-to-PCB inductance and improving thermal performance.
In order to meet environmental requirements, ST offers the ST54J devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark
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|ST54J-WLCSP||Evaluation : Product is under characterization. Limited Engineering samples available||-||-||DICE||Not Applicable||5A002A1||-||MORE INFO||No availability reported, please contact our Sales office|
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(**) The Material Declaration forms available on st.com may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.