Phase-Change Memory

Embedded Memory technologies are at a crossroads. The integration of conventional floating gate embedded Non-Volatile Memories (eNVM) represents a significant technical challenge at 28nm and smaller silicon geometries in both FD-SOI and FinFET advanced CMOS technologies. New NVM technologies, based on the functional properties of particular exotic materials, employ radically different physical mechanisms than those used with Flash memory technologies and provide a more effective solution to the process integration difficulties raised by the disruptive 28nm CMOS transition. Among these new NVM technologies, often called “emerging memories,” the most mature is Phase-Change Memory (PCM).

The fundamental mechanism for Phase-Change Memory was invented in the 1960s by Stanford Robert Ovshinsky. ST holds a license to the patents that resulted from that original development and has built onto that ground-breaking work for more than 15 years, developing the embedded PCM solution (ePCM) that is today integrated into our 28nm FD-SOI technology platform.

Phase-Change Memory is made using a Germanium Antimony Tellurium (GST) alloy, and takes advantage of rapid heat-controlled changes in the material’s physical property between amorphous and crystalline states. These states, which correspond to logic 0 and 1, are electrically differentiated by high resistance in the amorphous state (logic 0) and low resistance in the crystalline state (Logic 1). PCM, which reads and writes at low voltage, offers several substantial advantages over Flash and other embedded memory technologies.

phase change memory pcm storage mechanism

Phase-Change Memory Technology Architecture

Phase-Change Memory (PCM) array

phase change memory pcm array

A cross section of the embedded-PCM bitcell integrated in the 28nm FD-SOI technology shows the heater that quickly flips storage cells between crystalline and amorphous states.

Phase-Change Memory Advantages

Write Performance / Data Retention

With single-bit alterability, PCM technology delivers significantly better write and comparable read performance than Flash-based memories that require at least a byte- or sector-erase cycle before reprogramming. This single-bit alterability simplifies software handling of data storage. ST’s implementation benefits from patented technology related to the memory cell and to the GST alloy to support high-temperature data retention, including during solder reflow, so firmware can be uploaded to ePCMs before mounting and soldering.

High Density / Low Power Roadmap

The speed/power characteristics of the ePCM macro-cell and its roadmap at smaller geometries offer a scalable solution for large embedded memories.

Robust Performance

ST’s PCM technology has been developed and tested to operate within the most stringent automotive requirements for robust high-temperature operation, radiation hardening, and data retention. ePCM achieves automotive requirements for AEC-Q100 Grade 0 with an operating temperature up to +165°C.

Flexible Back-end Process

ePCM is a back-end technology which separates the non-volatile memory-cell process module from the complex logic-transistor modules built in the Front-End. As a Back-End, metallization-based process, ePCM is technology-independent, so it can be embedded in virtually any technology node.

FD-SOI and PCM Combined

Fully Depleted Silicon On Insulator, or FD-SOI, another technology that ST pioneered, is a planar process technology that delivers the benefits of reduced silicon geometries while actually simplifying manufacturing. Combining 28nm FD-SOI and PCM enables memory array sizes that are 4-5 times larger than what Flash on bulk 40nm CMOS can achieve.

Phase-Change Memory Applications

Ever more demanding applications are pushing the limits of MCU architectures due to their need for more processing power, lower power consumption, and larger memory sizes. One of the most challenging demands is for larger embedded memories to hold bigger and more complex firmware.

ePCM presents a solution to these chip- and system-level challenges, while meeting automotive requirements for AEC-Q100 Grade 0, operating at temperature up to +165°C. In addition, ST’s technology assures firmware/data retention through high-temperature soldering reflow processes and immunity to radiation, for additional data safety.

ST presented an update on the architecture and performance of a 16Mb ePCM array for a 28nm FD-SOI automotive MCU at the 2018 International Electron Devices Meeting (IEDM) in San Francisco on December 4, 2018.

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