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STM32MP2 MPU series

64-bit microprocessors with neural processing unit

Next-gen STM32 microprocessors for Industry 4.0 and edge AI solutions

The STM32MP2 series is an industrial-grade 64-bit solution for secure Industry 4.0 and advanced edge computing applications that require high-end multimedia capabilities.

The STM32MP25 lines are the first of the STM32MP2 series.

Reaching up to 6,000 DMIPS, they support the growth of smart, connected applications thanks to robust features and a significant performance upgrade compared to previous generations. Samples of the STM32MP25 MPUs will be available at the end of this year.

0.8mm pitch package enabling 4L PTH PCB manufacturing.

    Robustness

  • 100% operating time for 10 years
  • Extended temperature up to +125°C
  • 10-year longevity program

    Connectivity

  • Time-sensitive networking (TSN)
  • Up to 3 gigabit Ethernet ports (with 2-port switch)
  • PCIe Gen2, USB 3.0, 3 x CAN-FD

    Strong security

  • SESIP Level 3 certification
  • TrustZone® on Cortex®-A and Cortex®-M
  • Robust hardware encryption

    Neural processing unit accelerator

  • 1.35 TOPS (tera operations per second)

    Multimedia

  • 1080p graphic capabilities (3D GPU, H.264 hardware video codec)
  • RGB, MIPI DSI, and LVDS displays

    Machine vision

  • MIPI CSI-2 camera interface with Lite-ISP
  • High neural processing capabilities
Industry 4.0
Machine learning
Smart homes
Smart metering
Payment terminals
Internet-of-things (IoT) and edge computing

Enabling flexible prototyping

  • An STM32MP25 evaluation board and discovery kit will be available in 2024.
  • Easier migration from existing platforms thanks to:
    • Mainlined open-source Linux distribution with Android support available via partners to ensure smooth software porting.
    • A common development framework: developers can use the same STM32Cube tools as for the STM32MP1 MPU series, including GCC-based IDEs, STM32CubeProgrammer, and STM32CubeMX. STM32CubeMX includes the DRAM interface tuning tool to simplify the configuration of the DRAM subsystem.
  • Our extensive third-party ecosystem will help developers accelerate their design.