Power Factor Correction is a technique of shaping input current to be as sinusoidal as possible to reduce harmonic distortion and associated losses and in-phase with input voltage in an AC circuit to have a power factor close to one.
Placed as a front end in relatively high-power switch mode power supplies (SMPS), a three-phase power factor corrector is designed with a number of different topologies to meet specific requirements. An interleaving architecture with two or more small interleaved stages is also useful to help achieve higher power densities. Or to further enhance efficiency of the combined PFC and rectifier front-end, bridgeless topologies have emerged that can help reduce conduction loss by minimizing the number of semiconductor switches in the line-current path. For high-power systems with higher current, both Continuous Conduction Mode (CCM) and Transition mode (TM) operations are required and a new patented approach with fixed off-time (FOT) operation can provide great advantages.
ST's extended offer of advanced PFC digital controllers and high-performance STM32 microcontrollers support interleaved and bridgeless topologies. To help design robust and high-efficient PFC stages, these devices embed all the required protection features including output overvoltage, brown-out, feedback disconnection and boost inductor saturation.
Developers will also appreciate our power MOSFETs and rectifiers including silicon-carbide (SiC) galvanically isolated gate drivers and a range of hardware and software evaluation and development tools.
阅读更多
Our products and solutions
ST's extended offer of advanced PFC digital controllers and high-performance STM32 microcontrollers support interleaved and bridgeless topologies. To help design robust and high-efficient PFC stages, these devices embed all the required protection features including output overvoltage, brown-out, feedback disconnection and boost inductor saturation.
Developers will also appreciate our power MOSFETs and rectifiers including silicon-carbide (SiC) galvanically isolated gate drivers and a range of hardware and software evaluation and development tools.
全部资源
| Resource title | 版本 | Latest update |
|---|
应用手册 (2)
| Resource title | 版本 | Latest update | ||
|---|---|---|---|---|
| 1.2 | 19 Dec 2019 |
19 Dec 2019
|
||
| 2.2 | 19 Mar 2021 |
19 Mar 2021
|
宣传册 (2)
| Resource title | 版本 | Latest update | ||
|---|---|---|---|---|
| 1.0 | 25 May 2021 |
25 May 2021
|
||
| 2.0 | 02 Jul 2021 |
02 Jul 2021
|
Magazine Articles (1)
| Resource title | 版本 | Latest update | ||
|---|---|---|---|---|
| 1.0 | 16 Nov 2018 |
16 Nov 2018
|
