STRADA770M is a dual-band 77 GHz radar transceiver with integrated FMCW chirp modulator and profiles-based chirps sequencer, targeting automotive radar applications, in both the 76-77 GHz and 77-81 GHz regulated frequency bands.
It is designed to be integrated in a full-blown radar sensor along with a controller/processor in charge of:
configuring it through the slave interface;receiving/processing the raw radar data (sampled IF from each RX channel) that it produces through the master interface.
The device is capable of synthesizing the low-phase-noise clock needed for optimal performance, with the help of an external 40 MHz or 50 MHz crystal, but supports an external oscillator as well.
Power can be provided to the device at a single supply voltage (3.3 V) or at two different ones (3.3 V and 2.6 V); in both cases additional voltages (1.2 V and, possibly, 2.6 V) are produced internally by means of integrated LDOs relying on up to 6 external passive stabilization networks.
A further external passive network is needed for implementing the loop filter for the internal modulator.
The device consists of the following main components:
a digital slave interface configurable at power-up time for SPI or I2C operation;a chirps sequencer capable of autonomously interleaving, over time, different chirp modulation/transmission/reception schemes as one-time-programmed by the external controller;a LO (Local Oscillator) linear frequency modulator (FMCW ramp generator);a set of 3 TX (transmit) channels, supporting per-chirp and per-channel power and binary phase control;a set of 4 RX (receive) channels, supporting per-chirp and per-channel gain and HP/LP filtering control and integrating high-speed/high-resolution ADCs and digital filtering/decimation;a digital master interface compliant to MIPI's D-PHY/CSI-2 v1.1 specifications, composed of 4 data lanes each one running at 480 Mbps or 600 Mbps (depending on main clock frequency) maximum data rate.
Those main components are complemented with:
single ended RF ports, for easier PCB and antennas implementation;provisions for coherent cascading of multiple instances of the device, for building systems with a greater number of TX/RX channels;detectors, monitors and diagnostic features enabling system-level implementation of ASIL-B functions;OTP memory for storing test-line calibration and tracking data.
The LO modulator support ramp slopes up to 50 MHz/μs.
TX channels are equipped with per-chirp- and per-channel-controllable binary phase shifters enabling MIMO radar systems and grant a maximum programmable output power of 10 dBm per channel, in worst case conditions (in the 76-77 GHz frequency range).
AEC-Q100 Grade 2 automotive qualification ongoing
Fan-Out Wafer Level BGA, 9x9 mm2, 0.5 mm pitch
2.6 V and 3.3 V voltage supplies
Integrated LDOs supporting single 3.3 V supply voltage
Integrated low-phase-noise oscillator, supporting 40 and 50 MHz crystals
Fully-programmable chirps sequencer with multi-profiles support
Fully-programmable FMCW chirp modulator
Three-channels transmitter(50 Ω single ended outputs)
Four-channels receiver(50 Ω single ended inputs)
Digital per-TX-channel power control
Binary per-TX-channel phase control
Digital per-RX-channel conversion gain control
Per-RX-channel programmable HP and LP filters
40/50 MHz 12-bits ADCs
Configurable SPI/I2C slave interface
MIPI D-PHY/CSI-2 (v1.1) digital output master interface (4 data lanes, up to 480/600 Mbps each, 1.92/2.4 Gbps aggregated)
Support for cascaded (master/slave) configurations
Integrated monitors, detectors, diagnostics for ISO26262 ASIL-B support