The chip is a fully integrated RF front-end able to support different bands (L1, L2, L5, L6 and L) thanks to a programmable and flexible RF-IF chain driven by a fractional PLL. In particular, G5RF is able to manage all the GNSS constellations available and planned in the next future like GPS, Galileo, Glonass, BeiDou, IRNSS and QZSS.
The RF_IF chain is followed from a 2-bit ADC able to convert the IF signal to Sign (SIGN) and Magnitude (MAG) bit. The MAG bit is internally integrated in order to control the variable gain amplifiers. The VGA gain can be also set by the SPI interface.
Further, it is able to manage L-band signal from 1525 to 1559 MHz, in this case a dedicated 10bit ADC is used and the SPI interface to transmit low data rate data in L band support.
A digital interface, JESD207 compliant, is used only to transmit GNSS data and clock to external baseband.
The embedded fractional PLL allows supporting a wide range of reference clocks (10 to 55 MHz) and generates a sampling clock available for the baseband.
The STA5635A embeds two LDOs to supply at 1.1 V the analog and digital cores of the device facilitating requirements to external power supply. A third LDO can be turned-on to supply at 1.8 V external active components as a TCXO.
The chip is manufactured in CMOS040nm Technology and housed in a QFN package.