产品概述
描述
These 32-bit automotive microcontrollers are a family of System-on-Chip (SoC) devices that contain many new features coupled with high performance 90 nm CMOS technology to provide substantial reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of this automotive controller family is built on Power Architecture® technology. This family contains enhancements that improve the architecture’s fit in embedded applications, includes additional instruction support for Digital Signal Processing (DSP), integrates technologies—such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system—that are important for today’s lower-end powertrain applications. The device has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device also has an External Bus Interface (EBI) for ‘calibration’.
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所有功能
- Single issue, 32-bit Power Architecture®Book E compliant e200z335 CPU core complex
- Includes Variable Length Encoding (VLE) enhancements for code size reduction
- 32-channel Direct Memory Access controller (DMA)
- Interrupt Controller (INTC) capable of handling 364 selectable-priority interrupt sources: 191 peripheral interrupt sources, 8 software interrupts and 165 reserved interrupts.
- Frequency-Modulated Phase-Locked Loop (FMPLL)
- Calibration External Bus Interface (EBI)1
- System Integration Unit (SIU)
- Up to 1.5 Mbyte on-chip Flash with Flash controller
- Fetch Accelerator for single cycle Flash access @80 MHz
- Up to 94 Kbyte on-chip static RAM (including up to 32 Kbyte standby RAM)
- Boot Assist Module (BAM)
- 32-channel second-generation enhanced Time Processor Unit (eTPU)
- 32 standard eTPU channels
- Architectural enhancements to improve code efficiency and added flexibility
- 16-channels enhanced Modular Input-Output System (eMIOS)
- Enhanced Queued Analog-to-Digital Converter (eQADC)
- Decimation filter (part of eQADC)
- Silicon die temperature sensor
- 2 Deserial Serial Peripheral Interface (DSPI) modules (compatible with Microsecond Bus)
- 2 enhanced Serial Communication Interface (eSCI) modules compatible with LIN
- 2 Controller Area Network (FlexCAN) modules that support CAN 2.0B
- Nexus Port Controller (NPC) per IEEE-ISTO 5001-2003 standard
- IEEE 1149.1 (JTAG) support
- Nexus interface
- On-chip voltage regulator controller that provides 1.2 V and 3.3 V internal supplies from a 5 V external source.
- Designed for LQFP144, and LQFP176
- Single issue, 32-bit Power Architecture®Book E compliant e200z335 CPU core complex
电路原理图
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EDA符号、封装和3D模型
STMicroelectronics - SPC563M64L5
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符号
封装
3D模型
质量与可靠性
| 产品型号 | Marketing Status | 封装 | 等级规格 | 符合RoHS级别 | 材料声明** |
|---|---|---|---|---|---|
| SPC563M64L5COAR | 批量生产 | LQFP 144 20x20x1.4 mm | 汽车应用 | Ecopack2 | |
| SPC563M64L5COAY | 批量生产 | LQFP 144 20x20x1.4 mm | 汽车应用 | Ecopack2 |
(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此，它们可能不是100%适用于特定的设备。有关特定设备的信息，请联系 销售支持。
样片和购买
| 产品型号 | 供货状态 | Budgetary Price (US$)*/Qty | 从ST订购 | Order from distributors | 封装 | 包装类型 | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | CPU Clock Frequency (MHz) (max) | Features set | 温度（ºC） | Flash Size (kB) (Data) | CPU Clock Frequency (MHz) (max) | Features set | Operating Temperature (°C) (min) | Flash Size (kB) (Data) | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 最小值 | 最大值 | |||||||||||||||||||
| SPC563M64L5COAR | | | distributors 无法联系到经销商，请联系我们的销售办事处 | LQFP 144 20x20x1.4 mm | Tape and Reel | MALTA | 5A991.b.4.a | NEC | 80 | - | -40 | 125 | - | 80 | - | -40 | - | |||
| SPC563M64L5COAY | | | distributors 无法联系到经销商，请联系我们的销售办事处 | LQFP 144 20x20x1.4 mm | Tray | MALTA | 5A991.b.4.a | NEC | 80 | - | -40 | 125 | - | 80 | - | -40 | - | |||
SPC563M64L5COAR 批量生产
SPC563M64L5COAY 批量生产