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The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
主要特性
- 150 MHz e200z4 Power Architecture core
- Variable length instruction encoding (VLE)
- Superscalar architecture with 2 execution units
- Up to 2 integer or floating point instructions per cycle
- Up to 4 multiply and accumulate operations per cycle
- Memory organization
- 4 MB on-chip flash memory with ECC and Read While Write (RWW)
- 192 KB on-chip RAM with standby functionality (32 KB) and ECC
- 8 KB instruction cache (with line locking), configurable as 2- or 4-way
- 14 + 3 KB eTPU code and data RAM
- 5 × 4 crossbar switch (XBAR)
- 24-entry MMU
- External Bus Interface (EBI) with slave and master port
- Fail Safe Protection
- 16-entry Memory Protection Unit (MPU)
- CRC unit with 3 sub-modules
- Junction temperature sensor
- Interrupts
- Configurable interrupt controller (with NMI)
- 64-channel DMA
- Serial channels
- 3 × eSCI
- 3 × DSPI (2 of which support downstream Micro Second Channel [MSC])
- 3 × FlexCAN with 64 messages each
- 1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
- 1 × eMIOS
- 24 unified channels
- 1 × eTPU2 (second generation eTPU)
- 32 standard channels
- 1 × reaction module (6 channels with three outputs per channel)
- 2 enhanced queued analog-to-digital converters (eQADCs)
- Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers
- 6 command queues
- Trigger and DMA support
- 688 ns minimum conversion time
- On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
- Nexus: Class 3+ for core; Class 1 for the eTPU
- JTAG (5-pin)
- Development Trigger Semaphore (DTS)
- Clock generation
- On-chip 4–40 MHz main oscillator
- On-chip FMPLL (frequency-modulated phase-locked loop)
- Up to 120 general purpose I/O lines
- Individually programmable as input, output or special function
- Programmable threshold (hysteresis)
- Power reduction mode: slow, stop and stand-by modes
- Flexible supply scheme
- 5 V single supply with external ballast
- Multiple external supply: 5 V, 3.3 V and 1.2 V
- Designed for LQFP176, LBGA208, PBGA324 and Known Good Die (KGD)
- 150 MHz e200z4 Power Architecture core
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EDA Symbols, Footprints and 3D Models
STMicroelectronics - SPC564A80B4
Speed up your design by downloading all the EDA symbols, footprints and 3D models for your application. You have access to a large number of CAD formats to fit with your design toolchain.
Symbols
Footprints
3D models
质量与可靠性
| 产品型号 | Marketing Status | 封装 | 等级规格 | 符合RoHS级别 | 材料声明** |
|---|---|---|---|---|---|
| SPC564A80B4CFAR |
批量生产
|
PBGA 324 23x23x1.82 | 汽车应用 | Ecopack2 |
|
SPC564A80B4CFAR
Package:
PBGA 324 23x23x1.82Material Declaration**:
(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此，它们可能不是100%适用于特定的设备。有关特定设备的信息，请联系 销售支持 。
样片和购买
| 产品型号 | 从分销商订购 | 从ST订购 | 供货状态 | ECCN (US) | ECCN (EU) | 包装类型 | 封装 | 温度（ºC） | CPU Clock Frequency (MHz) (max) | Flash Size (kB) (Data) | Features set | Country of Origin | Budgetary Price (US$)*/Qty | 更多信息 | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 最小值 | 最大值 | |||||||||||||||
| SPC564A80B4CFAR | 1 distributors |
批量生产
|
5A991B4A | NEC | Tape And Reel | PBGA 324 23x23x1.82 | -40 | 125 | 150 | - | Flexray | MALAYSIA | 18.6 / 1k | |||
供货状态
批量生产ECCN (US)
5A991B4ABudgetary Price (US$)*/Qty
18.6 / 1k