SR6G7C3

建议

SR6 G7 line of Stellar integration MCUs 32-bit Arm® Cortex®-R52, Cortex®-M4 automotive MCU 6x cores, HW virtualization, 20.5 MB NVM (with 2x 19.5 MB "OTA X2" storage), HSM, ASIL-D

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产品概述

描述

Stellar integration MCUs have been designed to meet the requirements of domain controllers and ECUs with high integration requested in the architectures of connected update-able automated and electrified cars. They have superior real-time and safe performance (with highest ASIL-D capability). Bringing HW based virtualization technology to MCUs, they ease the development and integration of multiple source SW onto the same HW while maximizing the resulting SW performance. They offer high efficiency OTA reprogramming capability with fast new image download and activation at almost no memory overhead thanks to SR6 unique built-in dual image storage tailored to OTA reprogramming needs and provide high speed security cryptographic services, for instance for network authentication.
  • 所有功能

      • AEC-Q100 automotive qualification on going
      • Stellar integration MCUs:
        • Have superior real-time and safe performance (with highest ASIL-D capability)
        • Bring HW based virtualization technology to MCUs for simplified multiple SW integration at optimized performance
        • Have built-in fast and cost effective OTA reprogramming capability (with built-in dual image storage)
        • Offer high speed security cryptographic services, for example for network authentication
    • Cores
      • 32-bit Arm® v8-R compliant CPU cores:
        • 6 Cortex®-R52 cores (4 of them with checker cores, 2 in split-lock configuration) allowing usage as either 6 cores (4 of them in lockstep configuration) or 5 cores (all of them in lockstep configuration), single precision FPU, new privilege level for real-time virtualization
        • 2 NEON extensions (for example SIMD, dual precision FPU)
      • 2 Cortex®-M4 multi purpose accelerators (data move and [pre]-processing). 1 in lockstep configuration
      • 4 eDMA engines in lockstep configuration
    • Memories
      • Up to 20.5 MB on-chip NVM non volatile memory
        • PCM (phase change memory) as non volatile memory
        • 19.5 MB code NVM, with embedded memory replication for OTA (over-the-air) reprogramming with up to 2x 19.5 MB
        • 1024 KB HSM dedicated code NVM
      • 640 KB data NVM (512 KB + 128 KB dedicated to HSM)
      • Up to 8576 KB on-chip general-purpose SRAM
    • Security: hardware security module - 2nd generation
      • On-chip high performance security module with EVITA full support
      • Symmetric and asymmetric cryptography processor
      • High performance lock-stepped AES-light security sub-system for fast ASIL-D cryptographic services
    • Safety: comprehensive new generation ASIL-D safety concept
      • New state of the art safety measures at all level of the architecture for most efficient implementation of ISO26262 ASIL-D functionalities
      • Complete HW virtualization architecture build on Cortex®-R52 new privilege mode (best-in class SW isolation, real-time support for multiple virtual machine/applications)
    • Device stand-by / low power modes
      • Ultra low power: stand by mode for lowest quiescent current with optimized active subsystem (for example stand-by RAM) and wakeup capability
      • Smart low power: stand-by mode enhanced with active Cortex®-M4 subsystem and extended COM interfaces and ADC peripheral.
    • Peripheral, IOs, communication interfaces
      • 28 LINFlexD modules
      • 2 dual-channel FlexRay controllers
      • 10 queued serial peripheral interface (SPIQ) modules
      • 2 SENT modules (15 channels each)
      • 2 PSI5 modules (2 channels each)
      • Enhanced analog-to-digital converter system with
        • 12 separate 12-bit SAR analog converters (including one supervisor/safety ADC).
        • 4 separate 9-bit SAR analog converters (2 channels each) with fast comparator mode
        • One 9-bit SAR analog converter for device stand-by / low power mode
        • Interconnection with GTM timer for autonomous ADC/GTM subsystem operation
      • Advanced timed I/O capability
        • Generic timer module (GTM4154)
      • Communication interfaces
        • 2 ethernet controllers 100/1000 Mbps, compliant IEEE 802.3-2008: IPv4 and IPv6 checksum modules, AVB, VLAN and EMC optimized SGMII
        • 19 modular controller area network (MCAN) modules, and 1 time-triggered controller area network (M-TTCAN), all supporting flexible data rate (ISO CAN-FD)
    • External memory interfaces
      • 2 OctalSPI to support Hyperbus™ memory (Flash/RAM) devices
      • 1 SDMMC interface

EDA符号、封装和3D模型

STMicroelectronics - SR6G7C3

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质量与可靠性

产品型号 Marketing Status 封装 等级规格 符合RoHS级别 材料声明**
SR6G7C3A0xxCxxx
建议
FPBGA 292 17x17x0.8 工业 -

SR6G7C3A0xxCxxx

Package:

FPBGA 292 17x17x0.8

Material Declaration**:

Marketing Status

建议

Package

FPBGA 292 17x17x0.8

Grade

Industrial

RoHS Compliance Grade

-

(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此,它们可能不是100%适用于特定的设备。有关特定设备的信息,请联系 销售支持

样片和购买

产品型号
从分销商订购
从ST订购
供货状态
ECCN (US)
ECCN (EU)
包装类型
封装
温度(ºC) CPU Clock Frequency (MHz) (max)
Budgetary Price (US$)*/Qty
更多信息
最小值
最大值
SR6G7C3A0xxCxxx 无法联系到经销商,请联系我们的销售办事处
建议
- - - FPBGA 292 17x17x0.8 -40 105 400
更多信息

单价(US$):

-

Country of Origin:

-

SR6G7C3A0xxCxxx

供货状态

建议

ECCN (US)

-

Budgetary Price (US$)*/Qty

ECCN (EU)

-

包装类型

-

封装

FPBGA 292 17x17x0.8

Operating Temperature (°C)

(最小值)

-40

(最大值)

105

CPU Clock Frequency (MHz) (max)

400

Budgetary Price (US$)* / Qty

Country of Origin

-

(*) 建议转售单价(美元)仅用于预算用途。如需以当地货币计价的报价,请联系您当地的 ST销售办事处 或我们的 经销商