The M95128-DRE is a 128-Kbit serial EEPROM device operating up to 105 °C. The M95128-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2.
The device is accessed by a simple serial SPI compatible interface running up to 20 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95128-DRE is a byte-alterable memory (16384 × 8 bits) organized as 256 pages of 64 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic.
The M95128-DRE offers an additional Identification Page (64 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.
- Compatible with the Serial Peripheral Interface (SPI) bus
- Memory array
- 128 Kbit (16 Kbytes) of EEPROM
- Page size: 64 bytes
- Write protection by block: 1/4, 1/2 or whole memory
- Additional Write lockable Page (Identification page)
- Extended temperature and voltage range
- Up to 105 °C (VCCfrom 1.7 V to 5.5 V)
- High speed clock frequency
- 20 MHz for VCC ≥4.5 V
- 10 MHz for VCC ≥2.5 V
- 5 MHz for VCC≥ 1.7 V
- Schmitt trigger inputs for noise filtering
- Short Write cycle time
- Byte Write within 4 ms
- Page Write within 4 ms
- Write cycle endurance
- 4 million Write cycles at 25°C
- 1.2 million Write cycles at 85°C
- 900 k Write cycles at 105°C
- Data retention
- more than 50 years at105 °C
- 200 years at 55°C
- ESD Protection (Human Body Model)
- 4000 V
- RoHS-compliant and halogen-free (ECOPACK2®)
RoHS Compliance Grade
(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此，它们可能不是100%适用于特定的设备。有关特定设备的信息，请联系 销售支持 。