Cortex-M7 constraint speculative prefetch

The Cortex-M7 implements the speculative prefetch feature, which allows speculative accesses to normal memory locations (for example: FMC, Quad-SPI devices). When a speculative prefetch happens, it may impact memories or devices that are sensitive to multiple accesses (such as FIFOs, LCD controller). It may also disturb the traffic generated by another masters such as LCD-TFT or DMA2D with higher bandwidth consumption when a speculative prefetch happens. In order to protect normal memories from a speculative prefetch, it is recommended to change memory attributes from normal to a strongly ordered or to device memory thanks to the MPU. For more details about configuring memory attributes, refer to MPU setting example with STM32Cube HAL on Armv6 and Armv7 architectures.

Cortex-M33 and Cortex-M55 are respectively based on the Armv8-M and Armv8.1-M architectures (Cortex®-M55 processor supports Arm Protected Memory System Architecture (PMSA)). In both cases, the MPU is a component that is primarily used for memory region protection.

Although the concepts for the MPU operations are similar, the MPU in the Armv8-M architecture has a different programmers’ model to the MPU in previous versions of the M-profile Arm® architecture.

It is important to realize that all MPU registers are banked. If Arm TrustZone® is enabled, there is a set of MPU registers for the secure state, and a mirror set for the non-secure state. When accessing the MPU address between 0xE000 ED90 and 0xE000 EDC4, the type of MPU registers accessed is determined by the current state of the processor.

Non-secure code can access non-secure MPU registers and secure code can access secure MPU registers. Secure code can access non-secure MPU registers at their aliased address.

Secure access sees secure MPU registers, non-secure access sees non-secure MPU registers. Secure software can also access non-secure MPU registers using the alias address.

A normal memory type is intended to be used for MPU regions that are used to access general instruction or data memory. Normal memory allows the processor to perform some memory access optimizations, such as access reordering or merging. Normal memory also allows memory to be cached and is suitable for holding executable code. Normal memory must not be used to access peripheral MMIO registers. The device memory type is intended for that use. A normal memory definition remains mostly unchanged from the Armv7-M architecture.

A device memory must be used for memory regions that cover peripheral control registers. Some of the optimizations that are allowed to normal memory, such as access merging or repeating, are unsafe to a peripheral register.

The AMBA® 5 AXI, AMBA® 5 AHB, and AMBA® 4 APB protocols have signals that can report the privilege level of an access request to the system.

The Cortex-M55 processor supports these signals across the manager AXI (M-AXI), the peripheral AHB (P-AHB), and the external private peripheral bus (EPPB) interfaces for device memory. It also supports privilege reporting for normal memory on P-AHB. However, accesses to normal memory on M-AXI can be buffered and cached, allowing memory read and write requests, as well as instruction fetches from both privileged and unprivileged software, to be merged. For these transactions initiated by loads and stores, the AXI signals ARPROT[0] and AWPROT[0] are always 1 indicating a privileged access. Access permission to a region of memory can always be restricted to software running in privileged mode by using the MPU.

The instruction tightly coupled memory (ITCM) and data tightly coupled memory (DTCM) interfaces provide the following signals: ITCMPRIV, D0TCMPRIV, D1TCMPRIV, D2TCMPRIV, and D3TCMPRIV. These signals indicate the privilege of all memory accesses except the ones initiated by loads and stores.

The attribute indirection mechanism allows multiple MPU regions to share a set of memory attributes.

The MPU can be configured to support 0, 4, 8, 12, or 16 memory regions (security extension is included in the Cortex‑M55 processor. Memory protection can be duplicated between secure and nonsecure MPU (MPU_S and MPU_NS).)

The number of regions in the secure and nonsecure MPU can be configured independently, and each can be programmed to protect memory for the associated security state.

The following figure shows that MPU regions 1, 2, and 3 are all assigned to SRAM. Therefore, they can share cache-related memory attributes.

At the same time, regions 1, 2, and 3 can still have their own access permission, XN, and shareability attributes. This is required as each region can be used differently in the application.