The USART or LPUART is able to wake up the MCU from a low-power mode only when the peripheral supports the dual‑clock domain. The USART or LPUART can be clocked by a clock independent from the APB clock. This clock can be either the HSI, MSI, or LSE clock depending on the device.
The USART or LPUART can then receive data even if its clock is disabled and the MCU is in low-power mode.
USART/LPUART wake-up sources
Some transmit, receive, and error interrupts are used to wake up from low power modes. For the full list of these interrupts, refer to the USART and LPUART interrupts section in the product reference manual.
To enable the USART or LPUART to wake up the MCU from low-power mode, the UESM bit must be set in USART/LPUART_CR1 before entering a low-power mode.
How the USART/PLUART wakes up the STM32
Wake-up from a low-power mode when the internal oscillator is off
If the STM32 MCU is in a low-power mode, and the internal oscillator clock used as USART/LPUART kernel clock is switched off, when a falling edge on the USART/LPUART receive line is detected, the USART or LPUART requests the kernel clock to be switched on again. The internal oscillator clock is then used for frame reception:
If the wake-up event is verified, the STM32 MCU wakes up from low-power mode, and the data reception goes on normally.
If the wake-up event is not verified, the internal oscillator clock is switched off again, the STM32 MCU is not woken up and remains in low-power mode, and the kernel clock request is released.
The figures below show an example of a wake-up event programmed to an “address match detection" (see USART/LPUART internal oscillator clock off in low-power mode for details on tWUUSART and tWULPUART).Figure 1. Wake-up event verified (wake-up event = address match)
1 LPBAM means low-power background autonomous mode.
Wake-up from a low-power mode in SmartRun domain (SRD)
The STM32 MCUs that support the LPBAM, which allows the devices to be functional and autonomous in Stop 0, Stop 1, and Stop 2 modes (with no software running).
The USART/LPUART is also functional in Stop mode thanks to the autonomous mode. The APB clock is requested by the peripheral each time the USART/LPUART status needs to be updated. Once the USART or LPUART receives the APB clock, it generates either an interrupt or a DMA request, depending on the peripheral configuration.
If an interrupt is generated, the device wakes up from Stop mode. If no interrupt is generated, the device remains in Stop mode, but the kernel and APB clocks are still available for the USART/LPUART. All the autonomous peripherals are enabled in the RCC (reset and clock controller). If DMA requests are enabled, data are directly transferred to/from the SRAM thanks to the DMA, while the STM32 MCU remains in Stop mode.
Figure 3. Wake-up interrupt from SmartRun domain
USART/LPUART baudrate for a correct wake-up
The maximum USART or LPUART baudrate to correctly wake up the STM32 MCU from a low-power mode depends on the USART/LPUART kernel clock status (switched on or off).
USART/LPUART kernel clock switched on in low-power mode
In this case, there is no constraint on the maximum baudrate to wake up the MCU from a low-power mode. It is the same as in Run mode.
Internal oscillator clock used as USART/LPUART clock source
For some devices like STM32L0/L4, there are two ways to keep the internal oscillator clock switched on during a low-power mode:
Set the HSIKERON/MSIKERON bit in RCC_CR.
Set the UCESM bit in USART/LPUART_CR3.
This bit allows the USART/LPUART to request the clock all the time, and not only on START bit falling edge.
Note:
For consumption reasons, some products offer peripheral clock gating during Sleep and Stop modes. Consequently, for the USART and LPUART, the clock gating must be removed prior to entering in low-power mode. For more details, refer to the RCC section in the device reference manual,.
For STM32F0/F3 devices, the internal oscillator clock is always switched off during Stop mode. It is switched on only when a falling edge is detected on the USART/LPUART receive line.
LSE used as LPUART clock source
When the LSE clock is used as LPUART clock source, the maximum baudrate is 9600 bauds.
The LSE clock remains switched on in low-power mode, but, for STM32L0/L4 devices, it is not propagated to the LPUART if the LPUART does not request this kernel clock. To correctly receive data at 9600 bauds during a low-power mode, the UCESM bit must be set in LPUART_CR3: this bit allows the LPUART to request the clock at any time, not only on the START bit falling edge.
For the other STM32 devices, the LSE clock remains switched on in low-power mode, and is propagated to the LPUART. There is no constraint to receive data at 9600 bauds.
LSE used as USART clock source
When the LSE clock is used as USART clock source, the maximum baudrate is:
