USART/LPUART internal oscillator clock off in…

USART/LPUART internal oscillator clock off in low-power mode

If the internal oscillator clock is switched off during a low-power mode, the maximum baudrate to correctly wake up an STM32 MCU from a low-power mode depends on the following criteria:

the wake-up time parameter (t_WUUSART or t_WULPUART)
- For STM32F0/F3/L0 devices, t_WUUSART (or t_WULPUART) equals t_WUSTOP (as specified in the datasheet).
- For the other STM32 devices, t_WUUSART (or t_WULPUART) is specified in the datasheet.

the USART receiver tolerance, which depends on the following parameters:

9-, 10-, or 11-bit character length, configured through the M bits in USART_CR1
oversampling by eight or 16, configured through the OVER8 bit in USART_CR1
BRR[3:0] = or ≠ 0 in USART_BRR

one or three sample bits used to sample data, depending on ONEBIT in USART_CR3

The tables below summarize the USART receiver tolerance according to the values of the above parameters.

Table 4. USART receiver tolerance when BRR[3:0] = 0x0
M bits	USART receiver tolerance (%) when OVER8 = 0		USART receiver tolerance (%) when OVER8 = 1
M bits	ONEBIT = 0	ONEBIT = 1	ONEBIT = 0	ONEBIT = 1
00	3.75	4.375	2.5	3.75
01	3.41	3.97	2.27	3.41
10	4.16	4.86	2.77	4.16

Table 5. USART receiver tolerance when BRR[3:0] ≠ 0x0
M bits	USART receiver tolerance (%) when OVER8 = 0		USART receiver tolerance (%) when OVER8 = 1
M bits	ONEBIT = 0	ONEBIT = 1	ONEBIT = 0	ONEBIT = 1
00	3.33	3.88	2	3
01	3.03	3.53	1.82	2.73
10	3.7	4.31	2.22	3.33

the LPUART receiver tolerance, which depends on the following parameters:

number of Stop bits configured through STOP[1:0] bitfield in LPUART_CR2

value of LPUART_BRR

The table below summarizes the LPUART receiver tolerance according to the values of the above parameters.

Table 6. LPUART receiver tolerance
M and Stop bits	LPUART receiver tolerance (%) when OVER8 = 0		LPUART receiver tolerance (%) when OVER8 = 1
M and Stop bits	ONEBIT = 0	ONEBIT = 1	ONEBIT = 0	ONEBIT = 1
8 bits (M = 00), 1 Stop bit	1.82	2.56	3.9	4.42
9 bits (M = 01), 1 Stop bit	1.69	2.33	2.53	4.14
7 bits (M = 10), 1 Stop bit	2.08	2.86	4.35	4.42
8 bits (M = 00), 2 Stop bits	2.08	2.86	4.35	4.42
9 bits (M = 01), 2 Stop bits	1.82	2.56	3.9	4.42
7 bits (M = 10), 2 Stop bits	2.34	3.23	4.92	4.42

The USART/LPUART asynchronous receiver works correctly only if the total clock system deviation is less than the USART/LPUART receiver tolerance. The following parameters contribute to the total deviation:

DTRA: deviation due to the transmitter error (also includes the deviation of the transmitter local oscillator)
DQUANT: error due to the baudrate quantization of the receiver
DREC: deviation of the receiver local oscillator
DTCL: deviation due to the transmission line (generally due to the transceivers, which introduce an asymmetry between the low‑to‑high and high‑to‑low transition timings)

The rule is then given by this formula

D T R A + D Q U A N T + D R A C + D T C L + D W U < U S A R T o r L P U A R T r e c e i v e r t o l e r a n c e

where DWU is the error due to sampling point deviation when the wake-up from a low-power mode is used.

The maximum baudrate to wake up the MCU from a low-power mode can be computed as follows:

case 1: USART/LPUART receiver with 9-bit data length and M = 01
${D W U}_{\max} = \frac{t_{W U U S A R T / W U L P U A R T}}{(11 \times T_{b i t \min})}$
where T_{bit min} is the minimum bit duration
$M a x i m u m b a u d r a t e = \frac{(11 \times {D W U}_{\max})}{t_{W U U S A R T / W U L P U A R T}}$
case 2: USART/LPUART receiver with 8-bit data length and M = 00
${D W U}_{\max} = \frac{t_{W U U S A R T / W U L P U A R T}}{(10 \times T_{b i t \min})}$

$M a x i m u m b a u d r a t e = \frac{(10 \times {D W U}_{\max})}{t_{W U U S A R T / W U L P U A R T}}$
case 3: USART/LPUART receiver with 7-bit data length and M = 10
${D W U}_{\max} = \frac{t_{W U U S A R T / W U L P U A R T}}{(9 \times T_{b i t \min})}$

$M a x i m u m b a u d r a t e = \frac{(9 \times {D W U}_{\max})}{t_{W U U S A R T / W U L P U A R T}}$

STM32L4 example

Conditions: USART receiver with OVER8 = 0, M = 10, ONEBIT = 1, and BRR[3:0] = 0x0.

In this case, the USART receiver tolerance is 4.86 % (refer to Table 4 USART receiver tolerance when BRR[3:0] = 0x0).

In the ideal case where DTRA = DQUANT = DREC = DTCL = 0%, DWU max = 4.86%. In reality, the HSI inaccuracy must be taken into account.

For an HSI inaccuracy of 1 %:

t_WUUSART = 8.5 μs (for Stop 1 or Stop 2 modes)
DWU_max = 4.86 - 1 % = 3.86 %
T_{bit min} = 8.5 / (9 x 3.86 %) = 24.4 μs

The maximum baudrate to correctly wake up the STM32 MCU from a low-power mode is then:

1 / 24.4 μs = ~ 40 kbauds.