AN5489

• The main I/Os voltage supply (V_DD) range is either 1.8 V or 3.3 V typ. There are as well dedicated independent I/Os supplies for some interfaces (V_DDIO1, V_DDIO2, VDDIO3, and V_DDIO4).
• There are multiple analog and digital logic voltage supplies, see Power supply schemes for details.
• The real-time clock (RTC) and backup registers can be powered from the V_BAT voltage when the main V_DD supply is powered off. This internal supply with automatic switch between V_BAT and V_DD is named V_SW domain and is also used to supply PI8, PC13, PZ0 to PZ5 pins, and, only for TAMP_IN usage, the PC3, PC4, PC5, PF6, PF7, PG1, PG3, and PZ6 pins.

  V_BAT voltage is typically 3 V when used with a coin-cell battery.

To make sure that the conversion of signals is more accurate and can cover a wider range of values, the ADC (analog-to-digital converter) and reference have their own power supply that can be filtered separately. This helps to protect them from any interference or noise that may be present on the printed circuit board (PCB).

The analog operating voltage supply (V_DDA18ADC) is 1.8 V typ.

• The ADC/VREFBUF voltage supply input is available on a separate VDDA18ADC pin.

• An isolated supply ground connection is provided on the VSSA pin.

  In all cases, the VSSA pin must be externally connected to the same supply ground as the V_SS.

To retain the content of the backup registers, BKPSRAM and RETRAM, when V_DD is turned off, the VBAT pin can be connected to an optional standby voltage supplied by a battery or another source.

The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (V_DD) is turned off. The switch to the V_BAT supply is controlled by the power down reset (PDR) circuitry embedded in the PWR.

If no external battery is used in the application, it is recommended to connect V_BAT externally to V_DD.

The circuit is powered by multiple power supplies. Those supplies must be connected to external decoupling capacitors (see Table 4 Amount of decoupling recommendation by package).

V_DDIO1, V_DDIO2, V_DDIO3, and V_DDIO4 have specific register settings and control sequences to be respected when used at 3 V/3.3 V or 1.8 V typ. Refer to the PWR section in the product reference manual for details.

See also I/O speed settings for constrains on I/O speed settings for V_DD, V_DDIO1, V_DDIO2, V_DDIO3, and V_DDIO4 domains.

The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.71 V.

The device remains in the Reset mode as long as V_DD and V_DD18AON are below a specified threshold, and V_POR/PDR is without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in the product datasheets.

The system has an integrated circuitry that allows proper startup operation of the V_DDCORE (D2) domain.

The V_DDCORE domain remains in Reset mode when V_DDCORE is below the operation threshold vddcore_ok. Once the V_DDCORE supply level is above the operation threshold vddcore_ok, the V_DDCORE domain is taken out of reset. When the LVDS_D2 bit is set, the V_DDCORE supply level can be lowered in LPLV-Stop1 or LPLV-Stop2 modes.

For more details concerning the vddcore_ok reset threshold, refer to the electrical characteristics of the datasheet.

The system has a detection circuitry, which detects if the V_DDCORE supply voltage is below or above the operating range. Detection is done by comparing the V_DDCORE with two thresholds (high and low thresholds).

VCOREH and VCOREL flags are available in the PWR control register 5 (PWR_CR5) to indicate if VDDCORE is higher or lower than the thresholds. The VCOREH and VCOREL are available on tamper signals but also connected to the EXTI2 and can generate an interrupt if enabled through the EXTI2 registers.

The detection is enabled by setting the VCOREMONEN bit in PWR control register 5 (PWR_CR5).

The VDDCORE voltage thresholds, when enabled, are not available in LPLV-Stop1, LPLV-Stop2, Standby1, Standby2, and V_BAT modes.

For more details concerning the vcore_thr_high and vcore_thr_low threshold, refer to the electrical characteristics of the datasheet.

The system has an integrated circuitry that allows proper startup operation of the V_DDCPU (D1) domain.

The V_DDCPU domain remains in Reset mode when V_DDCPU is below the operation threshold vddcpu_ok. Once the V_DDCPU supply level is above the operation threshold vddcpu_ok, the V_DDCPU domain is taken out of reset. When the LVDS_D1 bit is set, the V_DDCPU supply level can be lowered in LPLV-Stop1 or LPLV-Stop2 mode. For more details concerning the vddcpu_ok reset threshold, refer to the electrical characteristics of the datasheet.

The system has a detection circuitry, which detects if the V_DDCPU supply voltage is below or above the operating range. Detection is done by comparing the V_DDCPU with two thresholds (high and low thresholds). The level of the low threshold can be selected by the VCPULS bits in the PWR control Register 6 (PWR_CR6). The high level is fixed.

VCPUH and VCPUL flags are available, in the PWR control register 6 (PWR_CR6), to indicate if V_DDCPU is higher or lower than the thresholds. The VCPUH and VCPUL are available on tamper signals but also connected to the EXTI2 and can generate an interrupt if enabled through the EXTI2 registers.

The detection is enabled by setting the VCPUMONEN bit in PWR control register 6 (PWR_CR6). The VDDCPU voltage thresholds, when enabled, are not available in Run2, LPLV-Stop1, LPLV-Stop2, Standby1, Standby2, and V_BAT modes.

For more details concerning the vcpu_thr_high and vcpu_thr_low threshold, refer to the electrical characteristics of the datasheet.

The system has an integrated circuitry (GPUVM) that enables monitoring the independent GPU supply V_DDGPU. VDDGPURDY indicates if the V_DDGPU independent power supply is higher or lower than the VDDGPUVM threshold.

The independent V_DDGPU supply is not considered as present by default, and logical and electrical isolation is applied to ignore any information coming from the V_DDGPU domain. The voltage monitor is disabled by default.

The output of the VDDGPU monitor is connected to an EXTI line and can generate an interrupt if enabled through the EXTI registers. The GPUVMO output interrupt is generated when the independent power supply drops below the VDDGPUVM threshold and/or when it rises above the VDDGPUVM threshold, depending on the EXTI line rising/falling edge configuration.

When the GPU is not used (V_DDGPU OFF) or on hold (V_DDGPU voltage reduced), a specific sequence should be used. Refer to the PWR section in the reference manual for details.

The user can monitor the voltage level of the PVD_IN pin using the PVD (Programmable voltage detector). This can be achieved by comparing the voltage of the PVD_IN pin to the internal V_REFINT (Internal voltage reference) level.

The PVD is enabled by setting the PVDE bit in the PWR_CR3 register.

A PVDO flag is available to indicate whether the PVD_IN pin is higher or lower than the threshold. This event is internally connected to EXTI1 and can generate an interrupt if enabled through the EXTI1 registers. The PVD output interrupt can be generated when PVD_IN drops below the PVD threshold. It can also happen when PVD_IN rises above the PVD threshold depending on the EXTI line rising or falling edge configuration. As an example, the service routine can perform emergency shutdown tasks.

Only VDD and VDDA18AON are monitored by default, as it is the only supplies required for all system-related functions. The other I/O supplies (V_DDIO1, V_DDIO2, V_DDIO3, V_DDIO4, V_DD33UCPD, V_DD33USB, and V_DDA18ADC) can be independent from VDD and can be monitored with peripheral voltage monitoring (PVM).

A GPVMO flag is available, in the PWR control register 1 (PWR_CR1), to indicate if all enabled independent power supplies are higher or lower than the PVM threshold. This event is internally connected to the EXTI1 and can generate an interrupt if enabled through the EXTI1 registers. The GPVMO interrupt can be generated when all enabled independent power supplies rise above the PVM threshold or when at least one enabled independent power supply drops below the PVM threshold, depending on the EXTI1 line rising/falling edge configuration. The PVM is not available in Standby1 and Standby2 mode.

The independent supplies (V_DDIO1, V_DDIO2, V_DDIO3, V_DDIO4, V_DD33UCPD, V_DD33USB, and V_DDA18ADC) are not considered as present by default, and logical and electrical isolation is applied to ignore any information coming from the peripherals supplied by these dedicated supplies.

• If these supplies are shorted externally to VDD, the application should assume they are available without enabling any peripheral voltage monitoring and the power isolation can be removed by setting the corresponding supply valid bits.
• If these supplies are independent from VDD, the peripheral voltage monitoring (PVM) can be enabled to confirm whether the supply is present or not.

The backup regulator voltage (V08CAP) can be monitored by comparing it with two threshold levels.

Two flags are available in the PWR control register 2 (PWR_CR2), to indicate if V08CAP is higher or lower than the threshold. The monitoring can be enabled/disabled with a MONEN bit in PWR control register 2 (PWR_CR2). As an example, the levels could be used to trigger a routine to perform emergency saving tasks. The monitoring, when enabled, is also available in Standby1, Standby2, and V_BAT modes. The flags are available on tamper signals.

An application reset (app_rst) is generated from one of the following sources:

• A reset from NRST pad
• A reset from a POR/PDR signal (generally called power-on reset)
• A reset from BOR signal (generally called brownout)
• A reset from one of the independent watchdogs (IWDG)
• A software reset from the RCC
• A failure on HSE, when the clock security system feature is activated
• A RETRAM CRC error reset
• A RETRAM ECC failure reset

A system reset (sys_rstn) is generated from one of the following sources:

• A reset from app_rstn signal (application reset)
• A reset from vcore_rstn signal
• A reset from vcpu_rstn signal when the D1 domain does not exit from Standby1/2

NRST pin is also activated when app_rstn is internally generated and low-level duration could be adapted using RPCTL.

The NRSTC1MS pin is activated when sys_rstn is generated. NRSTC1MS pin could be used to control supplies of external flash memory required for the first-level boot of CPU1 and which need a power cycle to ensure a platform reboot (for example, SD card). Low-level duration could be adapted using RPCTL.

Refer to the RCC section in the product reference manual for more details on reset coverage and configuration.

1. This is a very simplified view, only to give an overview of resets flows, it does not include all details. Details and specific behaviors are described in the product reference manual.

The package must be selected by considering the constraints that are strongly dependent upon the application.

The list below summarizes the more frequent constraints:

• Number of interfaces required

  Some interfaces might not be available on some packages.

  Some interfaces combinations might not be possible on some packages.

  Refer to product datasheets for details.

• PCB technology constraints

  Small pitch and high ball density could require more PCB layers and higher PCB class requiring stack-up with microvia (laser via) technology.

• Package height
• PCB available area
• Thermal constraints

  Larger packages have better thermal dissipation capabilities.

As a general rule, for each used interface, it is recommended to keep ball choices together as close as possible to ease PCB routing and to avoid potential timing issues.

In addition, to fulfill timings, I3C signals like SDA/SCL pairs must be chosen thanks to Table 10 I3C pins possible combinations.

In order to explore easily peripheral alternate functions mapping to pins, it is recommended to use the STM32CubeMX tool available on www.st.com.

1. This is a screenshot example. It is not specific to STM32MP25xx lines. The appearance can also differ with future STM32CubeMX versions.

Different clock sources can be used to drive the subsystems clocks:

• HSI oscillator clock (high-speed internal clock signal): 64 MHz typical
• MSI oscillator clock (multispeed internal clock signal): 16 or 4 MHz typical
• HSE oscillator clock (high-speed external clock signal): 40 MHz typical
• PLL1 dedicated to Cortex-A35 core
• PLL2 dedicated to DDR subsystem
• PLL3 dedicated to GPU¹
• PLL4/5/6/7/8 clocks
• PLL_DSI to generate the DSI clock (up to 2.5 GHz) ¹
• PLL_USB to generate the USB clock (480 MHz)
• PLL_COMBOPHY to generate the USB3DR (for SuperSpeed) or PCIE clocks (up to 5GHz)¹
• PLL_LVDS to generate the LVDS clock (up to 1.1 GHz)¹

The devices have two secondary clock sources:

• 32 kHz low-speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for automatic wake-up from the Stop/Standby modes.
• 32.768 kHz low-speed external crystal (LSE crystal) that optionally drives the real-time clock (RTCCLK)

Each clock source can be switched on or off independently when it is not used, to optimize the power consumption.

Refer to the reference manual and datasheet for the description of the clock tree, and for details of the possible clock frequencies.

The high-speed external clock signal (HSE) can be generated from two possible clock sources:

• HSE user external clock (see Figure 4 HSE external clock).
• HSE external crystal (see Figure 5 HSE crystal).

See also Clock for recommended implementation.

1. Refer to the application note AN6055_General_information.html#id_61425__entry_btn_w5w_cmb.

In this mode, an external clock source must be provided. It can have a frequency from 16 to 48 MHz (refer to the corresponding datasheets for actual max value).

The external digital (V_IL/V_IH) or analog (amplitude of 200 mV pk-pk minimum) clock signal with a duty cycle of about 50%, has to drive the OSC_IN pin.

• OSC_OUT is tied to GND (max 1 kΩ): HSE digital bypass
• OSC_OUT is tied to V_DDA18AON (max 1 kΩ): HSE analog bypass
• OSC_OUT high-Z or connected to a crystal: HSE crystal mode.

When utilizing a bypass, the activation of the external clock generator can be achieved through the PWR_ON feature for the purpose of power conservation (that is to say deactivated during Standby). In that case, the OSC_IN clock input must be stable within 10 ms after the PWR_ON rising edge occurs.

The external oscillator frequency ranges from 16 to 48 MHz.

The external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 5 HSE crystal. Using a 40 MHz crystal frequency is a good choice to get accurate USB high-speed clocks.

The crystal and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected crystal.

For C_L1 and C_L2 it is recommended to use NP0/C0G capacitors selected to meet the load requirements of the crystal. C_L1 and C_L2, have usually the same value. The crystal manufacturer typically specifies a load capacitance that is the series combination of C_L1 and C_L2. The PCB and pin capacitances must be included when sizing C_L1 and C_L2.

Refer to the application note AN5489_General_information.html and electrical characteristics sections in the product datasheet for more details.

In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. The external digital (VIL/VIH) or analog (amplitude of 200 mV pk-pk minimum) clock signal with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high-Z (see Figure 6 LSE external clock). The configuration of the bypass mode as well as the selection between the digital and analog is done within the RCC registers.

The LSE crystal is a 32.768 kHz low-speed external crystal. It has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The resonator and the load capacitors have to be connected as close as possible to the oscillator pins. The goal is to minimize output distortion and startup stabilization time. The load capacitance values C_L1 and C_L2 must be adjusted according to the selected oscillator. It is recommended to use medium-high or high drive on the LSE oscillator.

Refer to the application note AN5489_General_information.html and the electrical characteristics sections in the product datasheet for more details.

Details can be found in the product reference manual (See Table 2 Reference documents).

The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, an application reset can be generated.

The clock security system can be turned on using software. When this happens, the clock detector is turned on after a delay in the LSE oscillator startup. The detector is turned off when the oscillator stops. If there is a problem with the LSE oscillator clock, the RTC/TAMP clock source is stopped and the TAMP block is notified for security protection and system wake-up.

In the STM32MP23/25xx lines, different boot modes can be selected by means of the BOOT[3:0] pins and OTP settings.

The values on the BOOT pins are sampled by boot ROM after a reset. It is up to the user to set the BOOT[3:0] pins before reset exit to select the required boot mode. The BOOT pins could also be resampled later by software (for example by reading SYSCFG_BOOTCR.BOOT[3:0] field) or by the boot ROM when exiting the Standby mode. Consequently, they must be kept in the required boot mode configuration all the time.

Figure 8 Boot mode selection example shows an example of the external connection required to select the boot memory of the STM32MP23/25xx lines devices.

Despite all the recovery cases in software, there is a risk that with wrong or corrupted flash memory content (such as: user mistake, bad flash memory content programmed, power lost), the system might not start (also known as ‘bricked’).

Note that on empty flash memory, the boot code automatically switches to UART/USB connection.

It might be required to have a way to force use of UART/USB connection in order to enable board flash memory reprogramming (for example: after sale services, firmware update).

There are also cases of where initial boot is done on a different flash memory than regular boot (for example the initial boot from SD-Card, which copies binary data in another flash memory like serial NOR, serial NAND, eMMC, or SLC NAND). This is possible as the initial boot code could set relevant OTP bits to force future boot from the programmed flash memory (see Figure 10 Simplified boot flow). This allows a simplified and flexible mass production without intervention on BOOT pins. The typical connections examples for a final board are described in Figure 9 BOOT pins typical connection schematics.

The switches could be done by various ways: pushbutton, solder bridges, connector contacts, test points, and so on, but assumed ‘open’ by default during normal product boot to avoid current flow in external resistors.

Note that OTP configuration could force or forbid any of the boot sources in order to satisfy product security requirements.

This embedded bootloader is located in the boot ROM memory. During boot, the OCTOSPI, FMC, SDMMC, and USART peripherals operate with the internal 64 MHz oscillator (HSI).

The USB3DR high-speed device, however, can function only if an external clock (HSE) is present with a recommended frequency of 40 MHz (alternatively, 16, 19.2, 20, 24, 25, 26, 28, 32, 36, 40 or 48 MHz could be used with OTP settings and/or automatic frequency detection).

For additional information, refer to the USB DFU/USART protocols used in STM32MP1 series bootloaders AN5489_General_information.html.

The host/target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG, or SWD connector and a cable connecting the host to the debug tool.

Figure 11 Host-to-board connection shows the connection of the host to the evaluation board.

The STM32MP25xx lines core integrates the serial Wire/JTAG debug port (SWJ-DP). It is an Arm® standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and an SW-DP (2-pin) interface.

• The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-AP port
• The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the AHB-AP port

The two pins of the SW-DP are multiplexed with two of the five JTAG pins of the JTAG-DP.

To avoid any uncontrolled I/O levels, the STM32MP25xx lines embed internal pull-up and pull-down resistors on JTAG pins:

• NJTRST: Internal pull-up
• JTDI: Internal pull-up
• JTDO-TRACESWO: Internal pull-up
• JTMS-SWDIO: Internal pull-up
• JTCK-SWCLK: Internal pull-down

Figure 12 JTAG/SWD using Arm® JTAG 20 connector implementation example shows the connection between the STM32MP23/25xx lines and a standard JTAG/SWD connector.

Figure 13 JTAG/SWD/UART VCP using STDC14 connector implementation example shows the connection between the STM32MP23/25xx lines and an STDC14 connector including UART virtual com port connection.

Reference example for the STDC14 header is FTSH-107-01-L-DV-K-A.

The CoreSight™ cross-trigger interface (CTI) is available on pins as DBTRGI and DBTRGO.

DBTRGI could be generated by the external user signal. It could be programmed also inside CoreSight™ components to start/stop traces or enter specific cores in debug mode (break).

DBTRGO could be generated by CTI to see externally that a trigger condition is reached by one of the CoreSight™ components (core break, trace started, and so on.).

DBTRGO could be made available on PZ3, PZ4, and PZ6.

DBTRGI could be made available on PZ3, PZ4, and PZ6.

The PH4 pin has a specific BOOTFAILN behavior (see boot documentation for details):

• During the boot phase, in case of boot failure, the PH4 pin is set to low open-drain. The debug LED lights bright. Note that in most cases, without secure boot enabled, this fail is not visible as it immediately falls back to an UART/USB boot.
• During UART/USB boot, the PH4 pin toggles open-drain at a rate of few Hz until a connection is started. The debug LED blinks fast.
• With BOOT[3:0] = 0b0011 (development boot), PH4 is set to low open-drain. The debug LED lights bright.
• In all other cases, like normal boot, the PH4 pin is kept in its reset value. It means in high-Z until further software setting.

It is a good idea to put a red LED on PH4 as shown in Figure 15 PH4 LED connection (valid for VDD = 3.3V). In case of VDD= 1.8V, additional circuitry might be needed.

LEDs are useful for quick visual signaling of system activity. So, it is a good choice to use at least PH4 for quick low level boot error signaling. In most cases, the LED circuitry does not conflict with usage for other purposes (such as USBH_HS_OVRCUR, USB3DR_OVRCUR).

For technical reasons, it is mandatory to use a multilayer PCB with a separate layer dedicated to the ground (VSS), and another layer dedicated to power supplies like V_DD, V_DDCPU, and V_DDCORE. This provides good decoupling and a good shielding effect.

A preliminary layout of the PCB must separate the different circuits according to their EMI contribution. The aim is to reduce cross‑coupling on the PCB that is noisy high-current circuits, low-voltage circuits, and digital components.

Due to a large power and high frequencies involved in the STM32MP25xx devices, it is mandatory to use PCB with at least four layers and with dedicated power planes for V_SSx and V_DDx.

It is important to set the right output drive on I/Os to have sufficient rise and fall time. Moreover, it helps avoid any additional ringing and noise.

When there are no specific requirements for I/O speed, it is mandatory to set OSPEEDR to 0.

As a first approximation, the following drawing and tables could be used to choose quickly the right setting to apply according to signal frequency and capacitive load. This setting might need to be tailored in case of signal integrity issue.

Whenever one OSPEEDR value of two or three is used, related I/O compensation needs to be enabled in SYSCFG. There are five independent I/O compensations for each of the five independent I/O supplies: V_DD, V_DDIO1, V_DDIO2, VDDIO3, and V_DDIO4. Refer to the product datasheet and reference manual for more details.

Note that there are five independent I/Os voltage sections (V_DD, V_DDIO1, V_DDIO2, VDDIO3, or V_DDIO3), which, in some AFMUX settings cases, could be shared between different interfaces.

When V_DD, V_DDIO1, V_DDIO2, VDDIO3, or V_DDIO4 are working at 1.8 V, settings must be done in PWR_CR1.VDDIOxVRSEL (for VDD, VDDIO3 and VDDIO4) or PWR_CR7.VDDIO2VRSEL (for VDDIO2) or PWR_CR8.VDDIO1VRSEL (for VDDIO1). Without these settings, the I/Os are working in degraded mode.

A trade-off between the PCB cost and easy electrical connections has to be made. Below, examples are, either for four or six layers PCB with only PTH (suited for 0.8mm pitch package), or for six layers PCB with both PTH and laser drilled vias (suited for 0.5mm pitch package).

Note that some STM32MP25xx lines packages with an outer ball pitch of 0.5 mm provide power improved center ball matrix with depopulated matrix. It enables large PTH via in between balls.

This ensures better supply connection as well as optimized thermal conductivity than small buried laser drilled vias.

All the power supply and ground pins must be properly connected to the power supplies. These connections, including pins, tracks, and vias must have as low impedance as possible. This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.

ElectroStatic discharge (ESD) and electromagnetic interference (EMI) should be taken into account from the beginning of a product development as it could be very complex and expensive to add them later.

ESD and EMI are driven by global standards (such as IEC 61000, JESD 22) which in most countries require a certification to allow mandatory marking to be applied on a product (such as CE, FCC).

ESD and EMI are also driven by standardized interface certification or requirements (for example USB).

Although the STM32MP23/25xx lines embed device level ESD protection, the final product protection should be done by external components, more especially on interfaces having external user access in the final product (such as Ethernet, USB, SD-card). Some components provide ESD protection as well as EMI common-mode filtering (for example ECMF02-2AMX6 used on USB). Some examples of ESD/EMI protections are provided in STM32MP25x reference design examples.

For more details, refer to the application note AN5489_General_information.html about the EMC design guide.

Signals that do not allow negative injection, such as input/output signals on VSW supply, need to be handled with care to prevent undershoots. To avoid this, a series resistor (usually 22 Ω) can be added close to the signal source to match impedance, or a small capacitor (suited to the impedance and frequency of the signal) can be added near the input/output to reduce ringing. Refer to the product datasheet for more information.

For more details, refer to the application note AN5489_General_information.html about the EMC design guide.

The STM32MP25xx lines are designed for a wide range of applications and often a particular application does not use 100% of the resources.

To increase the EMC performance, unused clocks, counters, or I/Os should not be left free. For example, I/Os should be set to “0” or “1” (external or internal pull-up or pull-down to the unused I/O pins), and unused features should be “frozen” or disabled.

This section provides examples to help the user to connect major and critical interfaces to the devices. Examples apply also to the STM32MP23x lines whenever the feature is available.

Refer to Clocks.

Table 15. HSE BOM for oscillator or crystal

Components	Oscillator (OSC_OUT = logic 0)	Crystal (OSC_OUT = crystal pin)
X1	NZ2016SH 40 MHz	NX2016SA 40 MHz
R1	10 Ω	- (open)
R2	10 KΩ / 30 KΩ1	- (open)
R3	- (open) / 33 KΩ1	0 Ω
R4	1 KΩ	- (open)
C1	- (open)	6.8 pF
C2	- (open)	6.8 pF
C3	10 nF	- (open)

The NRST reset signal in Figure 2 Simplified reset pin circuit is active low. The reset sources include:

• Reset button
• Debugging tools via the JTAG connector

Refer to Reset and power supply supervisor.

The boot option is configured by setting permanent wires or switches: SW4 (BOOT3), SW3 (BOOT2), SW2 (BOOT1) and SW1 (BOOT0) and internal OTP. Refer to Boot configuration.

In case of the UART boot using one of the possible U(S)ARTx_RX pins (see Table 18 Minimum set of default pins used during boot ROM phase) to avoid a floating signal sent to the host until the initialization character is received and decoded by the boot ROM, it is required to have a 10 kΩ V_DD pull-up on the respective U(S)ARTx_TX pin.

The U(S)ART_RX pin used for boot or system console should not be left floating to avoid dummy serial characters decoding. This could be ensured either by defining an internal pull-up in a uBoot/Linux device tree, or using a 10 kΩ VDD pull-up on the board.

The table below shows the default pins used for each boot interface.

The reference design shows the connections between the STM32MP25xx devices and some standard connector (refer to Debug management).

The STPMIC25 automatically applies power cycling when its RST_N pin is activated (for example, button, system reset). However, in the case of entering an RMA state, the power cycling should not be done. A 0 Ω resistance between NRST and STPMIC25 RST_n pins could be provided and removed when using the procedure to enter an RMA state. Refer to Power supplies.

This reference design example targets a complex 3.3 V I/Os platform with DDR4 and high integration PMIC. Usually, all platform components can be powered by the PMIC. Full power supply control is supported thanks to PMIC I²C and side band signals. The Sleep mode, the Stop mode, and the Standby mode are supported. See PMIC documentation for details of PMIC components.

See Table 4 Amount of decoupling recommendation by package.

This reference design example targets a complex 1.8 V I/Os platform with low power LPDDR4 and high integration PMIC. Usually, all platform components can be powered by the PMIC. The full power supply control is supported thanks to PMIC I²C and side band signals. The Sleep mode, the Stop mode, and the Standby mode are supported as well as very-low power standby with LPDDR4 retention. See PMIC documentation for details of PMIC components.

1. PDR_ON must always be connected to VDDA18AON.

See Table 4 Amount of decoupling recommendation by package.

A 240 Ω 1% resistor should be connected between DDR_ZQ and V_SS. This resistor must not be shared with the ZQ resistors required on each DDR4 component.

In case of a 2x16-bit device, the impedance matching resistor network connected on the termination voltage (VTT) supply must be placed as close as possible to the last device. ‘Fly-by’ routing techniques must be used to avoid any impedance discontinuities. Values in the example below should work in most cases, but could be tailored to each side I/O drive strengths and PCB impedance.

A 240 Ω 1% resistor should be connected between DDR_ZQ and V_SS. This resistor must not be shared with one or more ZQ resistors required on the LPDDR4 component.

Note that a good signal integrity is dependent on board, GPIO strength settings (GPIO_OSPEEDR registers) and V_DD voltage.

When using V_DDIO1 = 1.8 V, a setting of VDDIOxVRSEL could be required to ensure the adequate speed on pins used on SDMMC1 outputs.

If needed, the impedance matching resistor should be placed as close as possible of the output driver pin. Values in the example below should work in most cases, but could be tailored to IO drive strengths and PCB impedance.

Before the V_{CC_SDCARD} shutdown (for example before a Standby mode), all signals going to the card must be set to 0 or high-Z by the SDMMC1 driver.

The example is independent from MPU I/O voltage V_DD and relies on variable VDDIO1 that could be set, either to 3.0 V/3.3 V, or 1.8 V typ. using one of the followings:

• SDVSEL1 (‘0’ or high-Z = 3 V/3.3 V (default), ‘1’ = 1.8 V) connected to an external regulator or other component managing the V_DDIO1 voltage.
• A regular GPIO output connected to an external regulator or other component managing the V_DDIO1 voltage.
• An I²C bus in case of use with PMIC.

If a programmable V_{DDIO_SDCARD} is not available in the platform, V_DDIO1 could be connected to V_{CC_SDCARD}. In that case, UHS-I is not supported.

Note that a good signal integrity is dependent on board, GPIO strength settings (GPIO_OSPEEDR registers), and V_DDIO2 voltage.

When using V_DDIO2 = 1.8 V, a setting of VDDIOxVRSEL could be required to ensure the adequate speed on pins used on SDMMC2 outputs.

If needed, the impedance matching resistor should be placed as close as possible of the output driver pin. Values in the example below should work in most cases, but could be tailored to IO drive strengths and PCB impedance.

Up to four 8 or 16-bit SLC NAND memory devices (CE# = FMC_NCE1, FMC_NCE2, FMC_NCE3 or FMC_NCE4) are supported.

Note that boot is only done on the SLC NAND memory device connected to FMC_NCE1.

As boot is always done in SPI mode, if the serial flash memory is set by the application in multiple data lines, or if the sector addressing has been changed, a power cycle on a serial flash memory supply is required after Reset or Standby mode exit.

When using V_DDIO3 (or V_DDIO4)= 1.8 V, a setting of VDDIOxVRSEL could be required to ensure the adequate speed on pins used on OCTOSPIM outputs.

If needed, the impedance matching resistor must be placed as close as possible of the output driver pin. Values in the example below work in most cases, but can be tailored to I/O drive strengths and PCB impedance.

Otherwise, the NRSTC1MS might be pulled low by memory internal protections when memory I/O supply is not present (which could cause some unwanted reset of other platform devices using the NRSTC1MS pin).

Refer to memory documentation to verify the memory reset pin requirements: especially the presence of internal power on reset and/or internal pull-up on the reset pin).

Note that a good signal integrity is dependent on board, GPIO strength settings (GPIO_OSPEEDR registers), and V_DDIO3 (or V_DDIO4) voltage.

When using V_DDIO3 (or V_DDIO4) = 1.8 V, a setting of VDDIOxVRSEL could be required to ensure the adequate speed on pins used on OCTOSPIM outputs.

Multiple USB options are possible. Examples are listed below:

• 1 × hi-speed USB device (Figure 32 USB hi-speed device with Micro-B connector example or Figure 33 USB hi-speed device with Type-C connector example)
• 1 × hi-speed USB device (Figure 32 USB hi-speed device with Micro-B connector example or Figure 33 USB hi-speed device with Type-C connector example) + 1 × USB hi-speed host (Figure 34 USB hi-speed host example)
• 1 × SuperSpeed USB host (Figure 35 USB SuperSpeed host connection example), see note below
• 1 × SuperSpeed USB dual-role (Figure 36 USB hi-speed/SuperSpeed dual role connection example)
• 1 × SuperSpeed USB dual-role (Figure 36 USB hi-speed/SuperSpeed dual role connection example) + 1 × USB hi-speed host (Figure 34 USB hi-speed host example)

Multiple hi-speed USB hosts using an external USB hub component is not described here.

For USB SuperSpeed COMBOPHY PCB routing recommendations, see PCI Express (PCIE).

A 200 Ω 1% resistor should be connected between USB3DR_TXRTUNE and V_SS.

Refer to the application note AN5489_General_information.html for details on VBUS detection with GPIO.

A 200 Ω 1% resistor should be connected between USBH_HS_TXRTUNE and V_SS.

A 200 Ω 1% resistor should be connected between USB3DR_TXRTUNE and V_SS.

A 200 Ω 1% resistor should be connected between COMBOPHY_REXT and V_SS.

This example supports dual role data (host or device) as well as a USB Power Delivery protocol on Common Criteria lines using UCPD.

A 200 Ω 1% resistor should be connected between USB3DR_TXRTUNE and V_SS.

A 200 Ω 1% resistor should be connected between COMBOPHY_REXT and V_SS (if SuperSpeed is used).

VBUS fixed divider should be tailored from the expected VBUS voltage to keep the ADC input voltage below 1.8V. Typical value of the divider is 1/15 (for VBUS up to 20V) or 1/30 (for VBUS up to 48V).

The maximum limit for VCONN in TCPP02 is 100mW. However, this reference cannot be used in complete compliance with USB SuperSpeed because the USB specification requires VCONN to provide at least 1W. Contact STMicroelectronics for latest recommended parts.

After power-up, TCPP02 does not advertise itself on CC1/CC2 lines as a Type-C UFP. A Type-A to Type-C cable might be necessary for flash memory programming sequence to ensure the host computer to act as a DFP and initiate the enumeration process required for boot ROM USB boot.

A 200 Ω 1% resistor should be connected between COMBOPHY_REXT and V_SS.

When using VDD = 1.8 V, a setting of VDDIOxVRSEL could be required to ensure the adequate speed on the pins used on the ETHx outputs.

If needed, the impedance matching resistors must be placed as close as possible of the output driver pin. Values in the example below works in most cases, but can be tailored to each side I/O drive strengths and PCB impedance.

Alternatively, if PHY allows it and if the RCC can provide a precise 50 MHz clock (to be checked with respect to HSE quartz frequency and RCC other peripheral/core clocks frequency settings), a 50 MHz ETH_CLK can be provided by the STM32MP23/25xx devices to the PHY, and REF_CLK is left unconnected on both sides. This saves BOM and area, as well as some power on some PHYs.

Note that a good signal integrity is dependent on board, GPIO strength settings (GPIO_OSPEEDR registers), and V_DD voltage.

When using V_DD = 1.8 V, a setting of VDDIOxRSEL could be required to ensure the adequate speed on pins used on ETHx outputs.

If needed, the impedance matching resistors should be placed as close as possible of the output driver pin. Values in the example below should work in most cases, but could be tailored to each side I/O drive strengths and PCB impedance.

A 200 Ω 1% resistor should be connected between DSI_REXT and V_SS.

Notice that when using two single-link displays (Figure 44 Dual-link panel connection with LVDS), it is only possible to have the same image (clone) with the requirement to have exactly the same display configuration (that is to say both displays must have the same timings requirements). It is not possible to output different images on each display.

A 200 Ω 1% resistor should be connected between CSI_REXT and V_SS.

When possible, each package has been optimized to provide easier length matching when differential balls pair signals are not directly on adjacent balls. Table 28 Package length matching values shows internal package track length difference xP minus xN/xM at ball level to be considered by the PCB tool. Ideal length matching is achieved when: PCB track length of xP-PCB track length of xN/xM-internal package track length difference (table below) = 0.