Low-power high-performance 8x8 multizone Time-of-Flight (ToF) sensor

The Rx (or collector) exclusion zone includes all module assembly tolerances. It is used to define the cover glass dimensions. The cover glass opening must be equal to or wider than the exclusion zone.

The detection volume represents the applicative or system FoV in which a target is detected, and a distance measured. The Rx lens or the Rx aperture determines the detection volume. It is narrower than the exclusion zone.

Figure 4 VL53L8CX pinout (bottom view) shows the pinout of the VL53L8CX.

The VL53L8CX pin description for the I²C and SPI configuration is given in Table 4 VL53L8CX pin description for I²C and SPI configuration. For the pins that support both I²C and SPI protocol, the I²C description is listed first and the SPI second.

Figure 5 Typical application schematic for I²C shows the application schematic of the VL53L8CX in I²C protocol configuration.

Note: Capacitors on the external supplies (AVDD, CORE_1V8, and IOVDD) should be placed as close as possible to the module pins.

Note: IOVDD must be set to ensure the host and the VL53L8CX operate at the same voltage levels for direct interfacing.

Figure 6 Typical application schematic for SPI shows the application schematic of the VL53L8CX in SPI protocol configuration.

Note: Capacitors on the external supplies (AVDD, CORE_1V8, and IOVDD) should be placed as close as possible to the module pins.

Note: IOVDD must be set to ensure the host and the VL53L8CX operate at the same voltage levels for direct interfacing.

This section describes the software interface of the device. The host customer application controls the VL53L8CX using an application programming interface (API). The API implementation is delivered to the customer as a driver (C code and reference Linux® driver). The driver provides the customer application with a set of high level functions that allow control of the VL53L8CX firmware. This includes control of items such as device initialization, ranging start/stop, and mode select.

The device requires three supplies to be fully operational (AVDD, IOVDD, CORE_1V8). The device stays in reset until all three supplies are applied. Power supplies may be applied in any sequence, or all at the same time.

To ensure proper operation of the module, the following minimum slew rates on the supplies (see Figure 9 Power up slew) must be met. This ensures correct operation of the power on the reset circuitry. The circuitry triggers at 0.9 V. However, the supplies should reach their operation levels in accordance with the slew rates listed in Table 6 Supply slew minimum limits.

This section specifies the control interface. The I²C interface uses two signals: serial data line (SDA) and serial clock line (SCL). Each device connected to the bus uses a unique address and a simple controller/target relationship exists.

Both SDA and SCL lines are connected to a positive supply voltage using pull-up resistors located on the host. Lines are only actively driven low. A high condition occurs when lines are floating and the pull-up resistors pull lines up. When no data is transmitted both lines are high.

The controller device performs the clock signal (SCL) generation and initiates data transfer. The I²C bus on the VL53L8CX has a maximum speed of 1 Mbit/s/s and uses a device 8-bit address of 0x52.

Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit, Ac for VL53L8CX acknowledge and Am for controller acknowledge (host bus controller). The internal data is produced by sampling SDA at a rising edge of SCL. The external data must be stable during the high period of SCL. The exceptions to this are start (S) or stop (P) conditions when SDA falls or rises respectively, while SCL is high.

A message contains a series of bytes preceded by a start condition and followed by either a stop or repeated start (another start condition but without a preceding stop condition) followed by another message. The first byte contains the device address (0x52) and also specifies the data direction. If the least significant bit is low (that is, 0x52) the message is a controller-write-to-the-target. If the lsb is set (that is, 0x53) then the message is a controller-read-from-the-target.

All serial interface communications with the Time-of-Flight sensor must begin with a start condition. The VL53L8CX module acknowledges the receipt of a valid address by driving the SDA wire low. The state of the read/write bit (lsb of the address byte) is stored and the next byte of data, sampled from the SDA, can be interpreted. During a write sequence, the second byte received provides a 16-bit index, which points to one of the internal 8-bit registers.

As data are received by the target, they are written bit by bit to a serial/parallel register. After each data byte has been received by the target, an acknowledge is generated, the data are then stored in the internal register addressed by the current index.

During a read message, the contents of the register addressed by the current index is read out in the byte following the device address byte. The contents of this register are parallel loaded into the serial/parallel register and clocked out of the device by the falling edge of SCL.

At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device (that is, the VL53L8CX for a write and the host for a read).

A message can only be terminated by the bus controller, either by issuing a stop condition or by a negative acknowledge (that is, not pulling the SDA line low) after reading a complete byte during a read operation.

The interface also supports autoincrement indexing. After the first data byte has been transferred, the index is automatically incremented by 1. The controller can therefore send data bytes continuously to the target until the target fails to provide an acknowledge or the controller terminates the write communication with a stop condition. If the autoincrement feature is used, the controller does not have to send address indexes to accompany the data bytes.

Timing characteristics are shown in Table 7 I 2 C interface - timing characteristics for fast mode plus (1 MHz) and Table 8 I 2 C interface - timing characteristics for fast mode (400 kHz). Refer to Figure 16 I 2 C timing characteristics for an explanation of the parameters used.

Timings are given for all process, voltage, and temperature (PVT) conditions.

This section specifies the SPI control interface used to control data transfer.

The communication interface is based on a 4-wire, serial, synchronous interface between the host (controller) and the VL53L8CX (target device). Refer to the schematics in Application schematics. The 4-wire interface comprises the following four signals:

• NCS: Chip select (active low)
• MCLK: Main serial clock
• MOSI: Main output secondary input, data output from controller
• MISO: Main input secondary output, data output from target

All signals are CMOS inputs/outputs. Their levels are in line with the IOVDD supply. The SPI modes supported are clock polarity = 1 and clock phase = 1. These modes correspond to data captured on a clock’s rising edge and data propagated on a falling edge. The controller selects the target device with the NCS. The NCS enables target transmission. It is an active low signal. After the device is selected with the falling edge of the NCS, an 8-bit command can be received. If the VL53L8CX has not been activated using the NCS chip select line, the MCLK input clock and MOSI signals are disregarded.

The falling edge (high to low transition) of the NCS signal is required to initiate an action. The transmission ends with the rising edge (low-to-high transition). This causes the end of data transfer, and resets the internal counter and command registers. All this reinitializes the serial communication.

While the register address is applied on the MOSI pin, the same information is mirrored on the MISO pin.

The NCS can be reset to a noncommunication state (high) at any time, including during a transaction. Should this happen, the device resets its internal state machine. Consequently, any ongoing communications are aborted. No internal changes to the registers occur, and the interface is ready to receive a new transaction again. However, the SPI target can tolerate the MCLK being interrupted. It can resume at any point in time, without specific duration limit.

During each SPI clock cycle, a full duplex data transmission occurs. The MOSI input is the data signal, provided by the host to the device. It carries both the address and data information in write mode. Only address information is in read mode. The controller sends a bit on the MOSI line and the target reads it. Concurrently, the target sends a bit on the MISO line and the controller reads it. This sequence is maintained even when only one-directional data transfer is intended.

The MISO output is the data signal, provided by the device to the host. It carries the data in read mode only, and the mode register content during the address setup. Any internal register that can be written to, can also be read from. There are also read-only registers that contain device status information. For example, design revision details. A read instruction from an unused register location returns the value 0x00. A read instruction from the manufacturer’s specific registers may return any value. A write instruction to a reserved or unused register location is illegal. The effect of such a write is ignored. Transmission may continue for any number of clock cycles. When complete, the controller stops toggling the clock signal, and typically deselects the target.

The write timing sequence is shown in Figure 17 SPI writing timing sequence. Once the NCS selects the device, the controller sends a write command to the VL53L8CX. The controller then provides a clock to output the status. The writing sequence starts with the MOSI initial value equal to 1. The address is sent first, and the data is sent afterwards. The most significant bit is sent first (big endian format). The address length is 15 bits. Data length is 8 bits.

If the host continues to transmit data beyond the first 8 data bits, then the target goes into autoincrement write mode. The autoincrement write timing sequence is shown in Figure 18 SPI autoincrement write sequence. The MOSI initial value is 1. The address is incremented automatically and internally by the target. Subsequent data bits correspond to incrementing addresses.

The controller sends the read command to the VL53L8CX. The controller then provides a clock to output the status.

In read mode, the target writes the data to the controller. Transmission is ended by the controller. The reading sequence starts with the first value of the MOSI equal to 0. The most significant bit is sent first (big endian format). Once the last bit of the address has been received, the device fetches the data internally. The device then presents the data onto the MOSI pin by the next falling MCLK edge (half the MCLK period). This enables the host to sample the data on the following rising edge. Once 8 bits of data have been received, the host sets the NCS high. This terminates the process. More details of the SPI read timing are shown in Figure 19 SPI read timing.

If the host continues to toggle the MCLK after the last data bit has been read, the target goes into autoincrement read mode. In this mode, the address is automatically incremented by the target, and the read data are transmitted sequentially to the controller on the MISO line. More details of the SPI autoincrement read mode are shown in Figure 20 SPI autoincrement read sequence.

The storage temperature (T_STG) is the ambient temperature at which the device can be stored with no voltage applied.

The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage.

The VL53L8CX is compliant with the ESD values presented in Table 14 ESD performance.

The current consumption values are given in Table 15 Current consumption.

• Typical values quoted are for nominal voltage, process, and temperature (23°C).
• Maximum values are quoted for the worst case conditions (process, voltage, and temperature), unless stated otherwise (85°C)

Table 18 I²C, SPI, INT, and SYNC summarize the digital I/O electrical characteristics.

Figure 21 Zone mapping in 4x4 mode shows the zone definition in 4x4 mode. There are 16 zones in total. They increment along a row first before starting a new row. The physical view is from the device top into the lens. The number of zones, as indicated in Figure 21 Zone mapping in 4x4 mode, corresponds to the zone IDs returned by the sensor.

Figure 22 Zone mapping in 8x8 mode shows the zone definition in 8x8 mode. There are 64 zones in total. They increment along a row first before starting a new row. The physical view is from the device top into the lens. The number of zones, as indicated in Figure 22 Zone mapping in 8x8 mode, correspond to the zone IDs returned by the sensor to the host.

The VL53L8CX module includes a lens over the Rx aperture, which flips (horizontally and vertically) the captured image of the target. Consequently, the zone identified as zone 0, in the bottom left of the SPAD array (see Figure 23 Effective orientation), is illuminated by a target. This target is located at the top right-hand side of the scene.

The following criteria and test conditions apply to all the characterization results detailed in this section unless specified otherwise:

• The specified target fills 100% of the FoV of the device (in all zones).
• Targets used are Munsell N4.75 (17%), Munsell N8.25 (54%), and Munsell N9.5 (88%).
• AVDD is 3.3 V, IOVDD is 1.8 V, and CORE_1V8 is 1.8 V.
• Nominal ambient temperature is 23°C.
• Maximum range capability is based on a 90% detection rate. ¹
• Range accuracy figures are based on 2.7 sigma. This means that 99.3% of measurements are within the specified accuracy.
• Tests are performed in the dark and at 2 W/m² target illumination (940 nm). A 2 W/m² target irradiance at 940 nm is equivalent to 5 kLux daylight.
• All tests are performed without cover glasses with a crosstalk margin set to 0 kcps.
• The sensor relies on default calibration data.
• The device is controlled through the API using the default driver settings.

Table 19 Maximum ranging capabilities when ranging continuously at 30 Hz shows the maximum ranging capability of the VL53L8CX under different conditions. Refer to Measurement conditions for the general test conditions.

Table 20 Maximum ranging capabilities when ranging continuously at 15 Hz shows the maximum ranging capability of the VL53L8CX under different conditions. Refer to Measurement conditions for the general test conditions.

Figure 24 Range accuracy vs distance illustrates how range accuracy is defined over distance.

Table 22 Maximum ranging capabilities when ranging with autonomous mode at 1 Hz – 4x4 – integration time 5 ms shows the maximum ranging capability of the VL53L8CX under different conditions. Refer to Measurement conditions for the general test conditions.

Table 23 Maximum ranging capabilities when ranging with autonomous mode at 1 Hz – 8x8 – integration time 5 ms shows the maximum ranging capability of the VL53L8CX under different conditions. Refer to Measurement conditions for the general test conditions.

Figure 25 Range accuracy vs distance illustrates how range accuracy is defined over distance.

Self-heating or a change in ambient temperature increases silicon temperature. This results in a range offset drift. This may be minimized by performing a periodic autocalibration, resulting in a typical drift of 0.1 mm/°C.

The autocalibration is done automatically when a new ranging session is started. A stop/start of the device is required if the device is already streaming.

The figures below give details of the VL53L8CX module. All values are given in millimeters.

The VL53L8CX contains a laser emitter and corresponding drive circuitry. The laser output is designed to meet Class 1 laser safety limits under all reasonably foreseeable conditions including single faults. This is in compliance with IEC 60825-1:2014.

Do not increase the laser output power by any means. Do not use any optics to focus the laser beam.

The VL53L8CX complies with:

• IEC 60825-1:2014​
• 21 CFR 1040.10 and 1040.11 except for conformance with IEC 60825-1:2014 as described in Laser Notice No.56, dated May 8, 2019​
• EN 60825-1:2014 including EN 60825-1:2014/A11:2021,​
• EN 50689:2021 except for the requirement of clause 5 from EN50689 regarding child appealing products. If designing a child appealing product, contact ST Technical Application Support.​

There are two types of product marking:

• The first is on the backside of the module as shown in Figure 27 Outline drawing (2/4).
• The second is on the corner of the module cap as shown in Figure 31 2D marking product code on module cap below.

Product marking on the corner of the module cap

This is a 2D marking. Note that the code aligns with pin C7 of the module and is not an indicator of pin 1.

The labeling follows STMicroelectronics' standard packing acceptance specification. The following information is on the inner box label:

• Assembly site
• Sales type
• Quantity
• Trace code
• Marking
• Bulk ID number

At the customer/subcontractor level, it is recommended to mount the device in a clean environment. To help avoid any foreign material contamination at final assembly level, the modules are shipped in a tape and reel format.

Sensor modules house numerous internal components that are susceptible to shock damage. If a unit is subject to excessive shock, is dropped on the floor, or a tray/reel of units is dropped on the floor, it must be rejected, even if no apparent damage is visible.

Handling must be done with nonmarring ESD safe carbon, plastic, or teflon tweezers. Ranging modules are susceptible to damage or contamination. The customer is advised to use a clean assembly process until a protective cover glass is mounted.

A maximum compressive load of 25 N should be applied on the module.

Moisture sensitivity is level 3 (MSL) as described in IPC/JEDEC JSTD-020-C.

For devices that are classified to the levels defined in JEDEC JSTD-020-C, JEDEC JSTD-033-C provides:

• Manufacturers and users with standardized methods for handling, packing, and shipping.
• Standardized methods for using moisture/reflow and process sensitive devices.

Table 25 Recommended solder profile and Figure 34 Solder profile show the recommended and maximum values for the solder profile.

Customers have to tune the reflow profile depending on the PCB, solder paste, and material used. We expect customers to follow the “recommended” reflow profile, which is specifically tuned for the VL53L8CX package.

For any reason, if a customer must perform a reflow profile, which is different from the “recommended” one (especially where the peak temperature is > 240°C), the new profile must be qualified by the customer at their own risk. The profile has to be within the “maximum” profile limit described in Table 25 Recommended solder profile.

The VL53L8CX is currently available in the format below. More detailed information is available on request.