Power management IC for MPU: 2 buck converters and 4 LDOs

The STPMIC1L has a non-volatile memory (NVM) that enables scalability to support a wide range of applications:

• Default output voltage, POWER_UP/POWER_DOWN sequences, protection behavior, auto turn-on functionality, and an I²C slave address.
• The STPMIC1LA, STPMIC1LB and STPMIC1LD are preprogrammed devices to support the STM32MP1x series application processor versions.
• Straightforward NVM reprogramming via I²C to facilitate mass production directly in target applications.
• Possibility to lock NVM content to prevent further reprogramming by writing LOCK_NVM bit.

All output voltages with Rank = 0 are by default programmed with 0 Dec (refer to Table 15 LDO output voltage settings and Table 16 Buck output voltage settings).

The startup sequence is split into six steps (Rank = 0 to Rank = 5).

Each buck converter or LDO regulator can be programmed to be automatically turned ON in one of these phases. Each rank phase is separated by a delay (1.5 ms, 3 ms, 4.5 ms, or 6 ms) programmed in the NVM:

• Rank = 0: rail not turned ON automatically, no output voltage appears after POWER-UP
• Rank = 1: rail automatically turned ON after 7 ms following a turn_ON condition
• Rank = 2: rail automatically turned ON after a further 1.5 ms (by default)
• Rank = 3: rail automatically turned ON after a further 1.5 ms (by default)
• Rank = 4: rail automatically turned ON after a further 1.5 ms (by default)
• Rank = 5: rail automatically turned ON after a further 1.5 ms (by default)

Whatever the STPMIC1L version, the AUTO_TURN_ON option is set.

STPMIC1L V_IN input current consumption with all supply pins connected to V_IN except V_LDO3IN = V_OUT2 = 1.25 V, V_IN = 5 V, V_IO = 3.3 V from LDO2OUT at T_j = + 25 °C, unless otherwise specified.

All parameters are specified at V_IN = V_BUCKxIN = V_LDOxIN = 5 V, except V_LDO3IN = V_OUT2, V_OUT1 = 1.25 V, V_OUT2 = 1.35 V, V_LDO5OUT = 3.3 V, V_LDO2OUT = 3.3 V, V_LDO3OUT = snk/src, V_LDO4OUT = 3.3 V, V_IO = V_LDO2OUT, T_j = -40 °C to +125 °C, with recommended BOM, unless otherwise specified.

The STPMIC1L has a wide input voltage range from 2.8 V to 5.5 V to supply applications typically by a 5 V DC wall-adaptor or a 1-cell 3.6 V Li-Ion / Li-PO battery.

The STPMIC1L provides all the regulators needed to power supply a STM32MP1x MPU, a DDR and a flash memory:

• 4 LDOs
• 2 step-down (buck) converters

LDO2 and LDO5 are general-purpose LDOs suitable for supplying MPU application peripherals.

LDO3 serves for DDR3, DDR3L, DDR4 memory termination (sink-source mode) or to support the general-purpose mode, which is typically suitable for supplying lpDDR3 or lpDDR4.

LDO4 is a fixed 3.3 V regulator designed to supply a 3V3 USB PHY circuit.

Enable/disable - each LDO can be enabled or disabled independently:

• Automatically during the POWER_UP or POWER_DOWN sequence depending on the NVM settings.
• By software (I²C access): Setting the EN bit in the related LDO control register.
• By PWRCTRLx pins state change: The PWRCTRLx pins need to be programmed by I²C to enable this feature.

VLDO OUT voltage setting - LDO output voltage can be set:

• Automatically during the POWER_UP or POWER_DOWN sequence depending on the NVM settings.
• By software (I²C access): Setting the V_OUT bit field in the related LDO control register.
• By PWRCTRLx pins state change: The PWRCTRLx pins need to be programmed by I²C to select the necessary output voltages to meet the MPU application requirements.

The LDO can be enabled or disabled as in normal operation. See the “Enable/ disable” description above.

Soft start: This feature aims to limit input inrush current during the LDO startup phase. LDO soft-start duration is defined by the t_SSLDO parameter.

See Figure 3 LDO startup/shutdown timings.

Output discharge: When LDO is disabled, a pull-down discharge is automatically enabled. It allows the LDO output voltage to discharge within a t_SDLDO time delay. The LDO output is low before disabling the next regulators in the next ranking slot. It is active by default. It can be disabled by software to put the LDO output in high impedance when LDO is disabled (LDOS_PD_CR register).

OCP and Hiccup management: Each LDO supports OCP and can operate in Hiccup mode. When the output load of the LDO exceeds the I_LDOLIM overcurrent limit threshold, the LDO starts decreasing the output voltage, limiting the output current to I_LDOLIM. If the overcurrent lasts more than t_{OCPDB_LDO}:

• An interrupt is generated (if the interrupt has been unmasked by software)
• Hiccup mode (default behavior): The LDO is turned OFF for the t_{HICCUP_DLY} duration and then turned ON again.
• Fail-safe mode (alternative behavior): The PMIC is turned OFF for the t_{HICCUP_DLY} duration and then turned ON again (or goes into FAIL_SAFE_LOCK state)

See Overcurrent (OCP) and Hiccup mode for details on OCP & Hiccup management.

LDO2 and LDO5 have programmable I_LDOLIM overcurrent limit thresholds. I_LDOLIM thresholds are programmed in the NVM_LDOS_IOUT_SHR NVM register.

The LDO3 is a multipurpose LDO with two operating modes:

• Normal mode – LDO3 works as a general-purpose LDO as well as LDO2, 5.
• Sink-source mode – LDO3 can regulate the output voltage working in sink source mode. This mode is dedicated to supplying the termination of DDR3/DDR3L or DDR4 IC memories with fixed output voltage. If LDO3 is used in this mode, LDO3IN must be powered from the output of BUCK2 (See Figure 6). The output voltage is fixed and follows VOUT2/2 even during the BUCK2 ramp-up and ramp-down phases. The overcurrent limitation works both during sink and source output current modes.

LDO4 can be dedicated to supply a USB HS analog PHY power domain.

The LDO4 output voltage is fixed at 3.3 V.

General description

The STPMIC1L includes two buck converters that are optimized to supply circuits with high current consumption and meet fast transient response requirements.

All converters are based on an adaptive constant-on-time controller (COT) that guarantees an excellent transient response and high efficiency across a wide range of operating conditions.

The switching frequency of the converter is typically 2 MHz in a steady-state CCM condition. In a typical MPU application:

• BUCK1 is primarily dedicated to supplying power to the VDDCORE domain.
• BUCK2 is primarily dedicated to supplying power to the VDDQDDR domain.

Enable/Disable: each buck converter can be enabled or disabled independently (same behavior as LDO: see LDO Common features)

V_OUT voltage setting: Output voltage can be set:

• Automatically during a POWER_UP or POWER_DOWN sequence depending on the NVM settings.
• By software (I²C access): Setting the V_OUT bit field in the related buck control register.
• By PWRCTRLx pins state change: The BUCKx converter behaves according to BUCKx_MAIN_CR and BUCKx_ALT_CR content setting. BUCKx_MAIN_CR or BUCKx_ALT_CR is selected by the PWRCTRL pin allocated to BUCKx (see section Power control management (PWRCTRLx) (PWRCTRLx)).

Forced PWM mode (CCM mode): Each buck can be forced to work in PWM mode to keep a constant frequency and low ripple.

Normal and forced PWM modes are activated by the two-bit PREG_MODE [1:0] register as follows:

00: Normal (or auto mode)

01: Reserved

10: Forced PWM (CCM)

11: Reserved

Clock synchronization and clock phase shifting: When all buck converters work in a steady state in CCM mode, they are synchronized to a clock and are shifted by 180° in the following order:

• 0°: BUCK1
• 180°: BUCK2

Dynamic voltage scaling (DVS): When the buck output voltage is increased/decreased dynamically by the software, the buck output voltage (V_OUT) is stepped up/down following the S_RBK slew rate.

When a lower V_OUT is set, part of the buck converter output energy is discharged from the output capacitor following the S_RBK slew rate, providing current back to the input supply capacitor. This operation improves the total power efficiency.

OCP and Hiccup management: Each buck converter supports OCP and can operate in Hiccup mode. When the output load of the buck exceeds the I_OUT max output current (related to inductor peak current limit threshold I_BKLIM), the PWM pulse is immediately stopped, and the buck starts to decrease the output voltage, limiting the output current. If the overcurrent lasts more than t_{OCPDB_BUCK}:

• An interrupt is generated (if the interrupt has been unmasked by software).
• Default behavior: The buck is turned OFF for tHICCUP_DLY duration and then turned ON again.
• Alternative behavior: The PMIC is turned OFF for tHICCUP_DLY duration and then turned ON again (or goes to FAIL_SAFE_LOCK state).

See Overcurrent (OCP) and Hiccup mode for details on OCP & hiccup management.

All buck converters have a programmable I_OUT max current threshold. I_OUT thresholds are programmed in the NVM_BUCKS_IOUT_SHR NVM register.

Output discharge: When the buck is disabled, a configurable pull-down (PD) discharge is automatically enabled. The buck output voltage discharges in t_{SD_BKtime} duration (with typical recommended BOM) so that the buck converter output voltage is low before disabling the next regulators in the next ranking slot. Four values are configurable by software at runtime: no pull-down, slow-PD, fast-PD and forced slow-PD by setting BUCKS_PD_CR. Fast discharge output can be modified by software in fast-PD when the buck is disabled, or it can be disabled by software to configure the buck converter output to high impedance when it is disabled. See Figure 7 Buck startup/shutdown timings which shows fast-PD and slow-PD behavior.

Startup sequence: When a buck is enabled, a startup delay (t_{SU_BCK}) occurs before the output voltage starts to rise, and is followed by a soft-start voltage ramp (t_{SS_BCK}). See Figure 7 Buck startup/shutdown timings.

V_IN is below V_{INPOR_Fall} (see VIN monitoring). No output state can be guaranteed in this state.

The INIT&LOAD state is immediately reached when V_IN is higher than V_{INPOR_Rise}.

STPMIC1L releases internal POR circuitry, it initializes, all registers are reset, the NVM load is performed (see Non-volatile memory (NVM)), and RSTn is asserted.

If the Auto_turn_on condition is true, PMIC makes a transition to the CHECK&LOAD state. Prior to leaving the INIT&LOAD state, the TURN_ON_SR is reset, and then the TURN_ON_SR[AUTO] bit is set.

If the Auto_turn_on condition is false, STPMIC1L evaluates the PONKEYn/EN status. If the turn on condition is not recognized, STPMIC1L makes the transition to the OFF state, otherwise it sets the proper bit in TURN_ON_SR and makes the transition to the CHECK&LOAD state (see Table 17 PMIC state machine transition conditions).

The OFF state is entered from the INIT&LOAD state, the POWER_DOWN state, or the FAIL_SAFE_LOCK state.

In the OFF state, the PMIC is in the lowest power consumption state, and all regulators are turned OFF. The voltage references are OFF and RSTn is asserted by PMIC.

All fail-safe counters are reset (xxx_FLT_CNT). Fail-safe timers (FLT_TMR), reset-fault-counter-timers (RST_FLT_CNT_TMR), and watchdog timers are stopped.

The transition to the CHECK&LOAD state (see Table 17 PMIC state machine transition conditions) is triggered by a turn-on condition (see Turn-on conditions).

Prior to leaving the OFF state, the TURN_ON_SR is reset, then the related turn-on condition bit is set in the TURN_ON_SR register.

CHECK&LOAD is a transitional state from a user point of view. It prepares the PMIC for power-up. The PMIC enables internal reference voltages, thermal monitoring, and V_IN monitoring.

The NVM is reloaded into shadow registers. Some registers are initialized with default values from the NVM content.

RSTn is asserted by the PMIC.

After the CHECK&LOAD state, the PMIC always transitions to the POWER-UP state if power-up conditions are fulfilled (see Table 17 PMIC state machine transition conditions) and the fault timer (FLT_TMR) ends. The fault timer waits before restarting the PMIC after a hard-fault (see OFF and CHECK&LOAD:).

The PMIC starts sequential regulators following a sequence that is predefined in the NVM and a default voltage that is predefined in the NVM (see ).

During the power-up sequence, RSTn is asserted by the PMIC. When the power-up sequence ends without a hard-fault, the PMIC releases RSTn signal.

In the POWER_ON state, the PMIC can be set to deliver power at full performance and features. Each regulator can switch power states (MAIN_CR or ALT_CR) depending on the PWRCTRLx pin settings (see Power control management (PWRCTRLx)).

The PMIC asserts RSTn, then sequentially turns off the regulators starting with the regulators not enabled in the power-up sequence (= rank0: enabled by software at runtime), then in reverse sequence order in the POWER_UP state (see POWER_UP / POWER_DOWN sequence).

When the POWER_DOWN sequence ends, before the transition to the next state, the watchdog is disabled (WDG_EN = 0) and status registers are updated according to the turn-off condition source:

• TURN_ON_SR and TURN_OFF_SR and RESTART_SR and OCP_SR1 and OCP_SR2 are reset (cleared)
• If RSTn is asserted by AP (PMIC transition to K in Table 17 PMIC state machine transition conditions):
  • RESTART_SR[R_RST] bit is set
• Else If SWOFF && RREQ_EN && PONKEYn set in NVM_MAIN_CTRL_SHR3 (PMIC transition to K in Table 17 PMIC state machine transition conditions):
  • RESTART_SR[R_SWOFF] bit is set
• Else If SWOFF && EN asserted && EN set in NVM_MAIN_CTRL_SHR3 (PMIC transition to K in Table 17 PMIC state machine transition conditions):
  • RESTART_SR[R_SWOFF] bit is set
• Else If EN asserted following a pulse deassertion on EN generating a turn-OFF condition (PMIC transition to K in Table 17 PMIC state machine transition conditions):
  • RESTART_SR[R_EN] bit is set
• Else If SWOFF && !RREQ_EN (PMIC transition to L in Table 17 PMIC state machine transition conditions):
  • TURN_OFF_SR[SWOFF] is set
• Else If EN deasserted (PMIC transition to L in Table 17 PMIC state machine transition conditions):
  • TURN_OFF_SR[EN] is set
• Else (it is a hard-fault turn-off condition, then depending on the hard-fault source):
  • If hard-fault is OCP:
    • OCP_SR1 or OCP_SR2 is updated with the OCP fault source
  • If PMIC transitions to M:
    • TURN_OFF_SR is updated with fault source
  • If PMIC transitions to K:
    • RESTART_SR is updated with fault source

The FAIL_SAFE_LOCK state is entered from the POWER_DOWN state with an M transition (a hard-fault counter xxx_FLT_CNT that exceeds the max number of PMIC restart occurrences xxx_FLT_CNT_MAX).

In the FAIL_SAFE_LOCK state, the PMIC is in the lowest power consumption state: All regulators are turned OFF, voltage references are OFF, and RSTn is asserted by the PMIC.

The PMIC is locked in that state until POR: a turn-on condition does not power-up the PMIC.

Nevertheless, the PMIC is allowed to skip the FAIL_SAFE_LOCK state in specific N transition conditions (see Table 17 PMIC state machine transition conditions).

The PMIC starts and stops regulators following the sequential 5 rank procedures called POWER_UP and POWER_DOWN, respectively.

During POWER_UP each regulator is started at one of the 6-rank phases programmed in the NVM. Each rank phase is separated by a delay (1.5 ms, 3 ms, 4.5 ms, and 6 ms) programmed in the NVM.

An additional delay can be programmed in the NVM to release the RSTn signal later than the last rank phase. This delay is also applied after the Turn_OFF condition, in between RSTn signal assertion and when the first regulator is powered off (RANK0).

The default rank sequence for each regulator, default output voltage of each regulator, default rank duration, and additional RSTn default delays are predefined in the NVM. Those values can be adapted by reprogramming the PMIC NVM with expected values.

An additional VIN_DLY [1:0] delay (0, 10 ms, 50 ms, 100 ms) can be programmed in NVM to prevent the PMIC from powering up, allowing VIN to stabilize.

^(*) The device remains in OFF state until a turn-on condition is triggered

For RANK_DLY and RST_DLY, see Table 132 NVM_MAIN_CTRL_SHR2

The PMIC is initially in NO_SUPPLY state with VIN < VINPOR_Fall. A power source is inserted making VIN rise. Once VIN > VINPOR_Rise, the PMIC goes into INIT&LOAD state. The PMIC reads NVM and performs internal initialization. Then, the PMIC launches the VIN_DLY [1:0] delay. Once the VIN_DLY elapses, the PMIC can transition to OFF state (or directly to CHECK&LOAD state if AUTO_TURN_ON bit is set in NVM).

The VIN_DLY is suitable when the PMIC starts immediately after VIN rise; especially when AUTO_TURN_ON bit is set in NVM.

The PMIC is initially in the OFF state. The RSTn pin is asserted by the PMIC. Once a turn-on condition occurs, the PMIC goes into the CHECK&LOAD state. As the turn-on condition is valid (for example: VIN>VINOK) the PMIC goes into the POWER_UP state.

In the POWER_UP state, RSTn is kept asserted by the PMIC.

The PMIC enables regulators sequentially by 1.5 ms slots (according to the default rank sequence and default output voltage defined in the NVM, RANK_DLY[1:0]).

For example (see Figure 9 PMIC POWER_UP and POWER_DOWN sequence example):

RANK1 (LDO2) then RANK2 (BUCK1) then RANK3 (GPO1) then RANK4 (LDO5) then RANK5 (GPO2).

Once the RANK5 ends, the PMIC releases RSTn and then it goes into the POWER_ON state.

In the POWER_ON state, all regulators are managed by the application processor’s software (I²C control) or by the PWRCTRL pin (see Power control management (PWRCTRLx)). In the example of Figure 9 PMIC POWER_UP and POWER_DOWN sequence example, BUCK2 is enabled by the AP’s software at runtime.

Once a Turn-OFF condition occurs, the PMIC asserts RSTn, then the PMIC shuts down RANK0 regulators that have been started by software (BUCK2 in the Figure 9 PMIC POWER_UP and POWER_DOWN sequence example example).

Then the PMIC disables the regulators sequentially in reverse rank order from the POWER_UP sequence, by 1.5 ms slots (according to the default rank sequence in the NVM, RANK_DLY [1:0]).

For example (see Figure 9 PMIC POWER_UP and POWER_DOWN sequence example):

RANK5 (GPO2), then RANK4 (LDO5), then RANK3 (GPO1), then RANK2 (BUCK1), then RANK1 (LDO2).

When the RANK1 ends, the PMIC goes into the OFF state (RSTn is kept asserted). The analog behavior of regulators is detailed in Power regulator descriptions.

The PONKEYn/EN pin is a multifunctional pin that can be configured (see PKEY_EN_CFG NVM pin) with two different functions: As PONKEYn, it is intended to be connected to a push-button at the application level. If the push-button is pressed by a user, the PONKEYn signal is grounded. If the push-button is released by the user, the PONKEYn signal is floating, but the internal PMIC R_PU ties PONKEYn to V_IN. When configured as Enable, it turns the PMIC on or off, based on the programmed polarity.

PONKEYn falling edge: the debounce filter timer is enabled once the PONKEYn voltage is lower than VIL. If a bounce voltage higher than VIH occurs, the debounce filter timer is canceled and so on.

PONKEYn rising edge: the debounce filter timer is enabled once the PONKEYn voltage is higher than VIH. If a bounce voltage lower than VIL occurs, the debounce filter timer is canceled and so on.

RPU and RPD settings are independent from the PONKEYn/EN configuration.

The RSTn is a bidirectional reset pin both for the PMIC and the application processor:

• Digital input: active low input reset (when not asserted by the PMIC). The application processor can assert RSTn low to force the PMIC to power cycle.
• Open drain output: The PMIC can assert RSTn low to reset the application processor, typically during a power-ON or a power-OFF sequence and a power cycling reset sequence. Pull-up (R_PU) is internally connected to V_IO.

The PMIC asserts INTn low when a PMIC interrupt is pending (and not masked):

• Digital output (open drain)
• Active low
• Pull-up (RPU) internally connected to V_IO.

Power control signals aim to control the regulator's behavior. Typically, power control signals are driven to ‘1’ or ‘0’ by the application processor to manage different power modes at application level.

PWRCTRLx pin characteristics:

The main input supply pin V_IN is monitored permanently by the PMIC state machine. There are different threshold triggers on V_IN. The lowest to the highest thresholds are: V_INPOR, V_INOK, and V_INLOW as shown in Figure 11 V IN monitoring thresholds.

V_INPOR is the minimum voltage required to supply the PMIC internal circuitry. It is specified by two hardcoded thresholds with 200 mV hysteresis:

Below V_{INPOR_Fall}, the PMIC is considered as not supplied.

Above V_{INPOR_Rise}, the PMIC internal circuitry is functional.

V_INOK is the minimal voltage required to allow the PMIC to work in the POWER_ON state.

It is specified by V_{INOK_Rise} threshold and V_{INOK_HYST} hysteresis values that can be adjusted in the NVM, respectively in the V_{INOK_RISE} [1:0] and V_{INOK_HYST} [1:0] bit fields.

If V_IN falls below V_{INOK_Fall} (V_{INOK_Fall} = V_{INOK_Rise} – V_{INOK_HYST}), then it is considered as a hard-fault turn-off condition and the PMIC immediately starts the POWER_DOWN sequence (see POWER_DOWN:). Following this condition, the PMIC waits for the t_{VINOK_Fall} delay before it can restart, even if V_IN exceeds V_{INOK_Rise} again before the t_{VINOK_Fall} delay ends.

Definition: The V_IN > V_INOK condition means that if V_IN rises above V_{INOK_Rise}, then V_IN remains higher than V_{INOK_Fall}. Reciprocally, V_IN < V_INOK means that V_IN < V_{INOK_Fall} or V_IN is less than the V_{INOK_Rise} threshold (this definition is just to simplify the state machine description).

V_INLOW operates as a flag to trigger an interrupt: V_{INLOW_Fall} and V_{INLOW_Rise} are configurable software thresholds that notify the AP (via an interrupt line) when the V_IN voltage crosses one of those two thresholds.

V_INLOW can be enabled and configured by programming the register V_{INLOW_CR}.

V_{INLOW_Rise} and V_{INLOW_Fall} thresholds generate, respectively, V_{INLOW_RI} and V_{INLOW_FA} interrupts, allowing the application processor to take relevant action. They can be unmasked independently.

The V_{INLOW_RI} interrupt is asserted once V_IN goes below the V_{INLOW_Rise} threshold.

The V_{INLOW_FA} interrupt is asserted once V_IN goes above the V_{INLOW_Fall} threshold.

A turn-on condition is required to power up the PMIC and to reach the POWER_ON state. A turn-on condition is only valid from the OFF state, or alternatively from the NO_SUPPLY state (the PMIC has no V_IN initially).

The PMIC manages several turn-on conditions:

• PONKEYn pin assertion or EN pin assertion
• AUTO turn-on (AUTO_TURN_ON bit set in the NVM, only if pin EN is not configured)
• Fail-safe restart condition

A turn-on condition can be triggered by an external signal source from PONKEYn/EN pin:

1. If PONKEYn is set in the PKEY_EN_CFG bit (NVM):
   1. PONKEYn is tied low initially. The PMIC is in a NO_SUPPLY state. When the V_IN voltage rises and crosses the V_{INPOR_Rise} threshold, the PMIC goes into the INIT&LOAD state (transition A), and then it goes into the CHECK&LOAD state (transition C).
   2. PONKEYn is initially released. The PMIC is in the OFF state. When the PONKEYn is asserted, a turn-on condition occurs.

2. If EN is set in the PKEY_EN_CFG bit (NVM):

- EN asserted: always a turn-on condition (except if PMIC is in FAIL_SAFE_LOCK state).

AUTO turn-ON allows the PMIC to be turned ON automatically when V_IN rises from V_IN < V_{INPOR_Fall}. An AUTO turn-ON event is triggered only from a NO_SUPPLY state transition:

1. V_IN rises from V_{INPOR_Fall} to V_{INPOR_Rise}
2. PMIC goes into INIT&LOAD state, then the AUTO_TURN_ON bit is enabled in the NVM
3. PMIC goes into the CHECK&LOAD state, waiting for V_IN>V_INOK
4. PMIC POWER_UP

The AUTO turn-ON is enabled in the NVM by default.

Turn-off conditions are triggered by events or stimulus leading the PMIC to perform a POWER_DOWN sequence.

Following the POWER_DOWN sequence, the PMIC can switch to the OFF state or to the FAIL_SAFE_LOCK state, or restart automatically (power cycle), depending on the source that has triggered the turn-off condition.

There are six sources triggering a turn-off condition detailed in Table 19 Turn-off condition trigger sources:

When the software sets the SWOFF bit, the PMIC starts a POWER_DOWN sequence immediately, then the PMIC goes into the OFF state. The TURN_OFF_SR is set accordingly.

PONKEYn set in PKEY_EN_CFG bit in NVM: If the software has set both the RREQ_EN and SWOFF bits, the PMIC restarts automatically after the POWER_DOWN sequence (transition K) and goes into the POWER_ON state. The RESTART_SR register is set accordingly.

EN set in PKEY_EN_CFG bit in NVM: If the software has set SWOFF bit while EN is asserted, the PMIC restarts automatically after the POWER_DOWN sequence (transition K) and goes into POWER_ON state.

The RESTART_SR register is set accordingly.

Each hard-fault source has a hard-fault counter: see Table 20 Hard-fault fail-safe counters and waits before restarting timer.

Each time a hard-fault event occurs, a turn-off condition is triggered, and it is managed by fail-safe management. See Fail-safe management.

Each hard-fault source has an independent fail-safe counter that is incremented each time a hard-fault turn-off condition occurs (see Table 20 Hard-fault fail-safe counters and waits before restarting timer). If the counter value is below (or equal to) the max limit, then the PMIC restarts (= power cycling on fault condition). Alternatively, if the counter is higher than the max limit, then the PMIC goes into the FAIL_SAFE_LOCK state to avoid cyclic hard failures.

Sequence details:

When a turn-off condition is triggered by a hard-fault source (see Table 19 Turn-off condition trigger sources):

• The corresponding hard-fault counter is incremented (see Table 20 Hard-fault fail-safe counters and waits before restarting timer): xxx_FLT_CNT ++
• The FLT_TMR is loaded with the corresponding hard-fault duration and starts (see Table 20 Hard-fault fail-safe counters and waits before restarting timer)
• The PMIC switches to the POWER_DOWN sequence
• Once the POWER_DOWN sequence ends:
  • If all counters xxx_FLT_CNT <= xxx_FLT_CNT_MAX then the PMIC goes into the CHECK&LOAD state, then PMIC waits for a FLT_TMR timer expiration before restarting (see Table 20 Hard-fault fail-safe counters and waits before restarting timer). Then it goes into POWER_UP, and then it goes in POWER_ON state. The corresponding bit in the RESTART_SR status register is set.
  • Else if one of the counters xxx_FLT_CNT > xxx_FLT_CNT_MAX, then PMIC goes into the FAIL_SAFE_LOCK state. The corresponding bit in the TURN_OFF_SR status register is set. Even when the FAIL_SAFE_LOCK is skipped, the PMIC waits for FLT_TMR expiration before restarting.
  Note: If EN set in PKEY_EN_CFG bit in NVM, it is assumed that EN is kept asserted during the above sequence.

Notes:

• 1 - When a counter (xxx_FLT_CNT [3:0]) reaches 0xF, all the next counter increments keep the counter value at 0xF (and not restart to 0). This allows for infinite PMIC restart iterations to be set when xxx_FLT_CNT_MAX [3:0] is set to 0xF.
• 2 - Setting 0 in xxx_FLT_CNT_MAX makes the PMIC go into the FAIL_SAFE_LOCK state after the first corresponding turn-off hard-fault condition (PMIC restarts 0 times).
• 3 - Setting 0xF in xxx_FLT_CNT_MAX makes the PMIC always restart after any corresponding urn-off fault condition as highlighted above in Note 1 (PMIC restarts indefinitely).
• 4 - Programming the NVM with t_{HICCUP_DLY} =‘0’ means no wait before restart.

To avoid reaching the FAIL_SAFE_LOCK state due to isolated turn-off hard-fault conditions, all counters can be reset automatically when no turn-off hard-fault condition occurs in RST_FTL_CNT_TMR timer duration (see Table 21 Reset fault counter timer settings for timer duration NVM settings).

From the NO_SUPPLY state and until a first turn-off condition occurs, the RST_FTL_CNT_TMR timer is disabled.

Each time a turn-off hard-fault condition occurs, the RST_FTL_CNT_TMR timer is reset to the RST_FLT_CNT_TMR[1:0] value and restarted.

When the RST_FTL_CNT_TMR timer elapses:

• All counters (*_FLT_CNT) are reset
• The RST_FTL_CNT_TMR timer is stopped until a new turn-off hard-fault condition occurs

If PMIC reaches the FAIL_SAFE_LOCK state before the RST_FTL_CNT_TMR timer elapses, then RST_FTL_CNT_TMR timer is reset and stopped.

A RSTn condition has no effect on the RST_FTL_CNT_TMR timer.

In the OFF state, the RST_FTL_CNT_TMR timer is reset and stopped, and all counters (*_FLT_CNT) are reset.

When the PMIC enters FAIL_SAFE_LOCK state, it remains in this state until PMIC POR (V_IN < V_{INPOR_Fall}).

Alternatively, there are three programmable options to force the PMIC to switch from the FAIL_SAFE_LOCK state to the OFF state:

• Set the bit FAIL_SAFE_LOCK_DIS in the NVM. It disables the FAIL_SAFE_LOCK feature (when the PMIC enters the FAIL_SAFE_LOCK state, it immediately transitions to the OFF state).
• A PKEY_EN_FAIL_SAFE_LOCK_SKIP condition
  • A PKEY_EN_FAIL_SAFE_LOCK_SKIP condition can be reached only if the PKEY_LKP_EN_FSLS (1) bit is set prior to entering the FAIL_SAFE_LOCK state (or if the NVM_PKEY_LKP_EN_FSLS bit is set in NVM, which automatically sets the PKEY_LKP_EN_FSLS bit) and:
  • A PONKEYn long key press event (if PONKEYn is set in the PKEY_EN_CFG bit (NVM))
  • An EN pin deassertion (if EN is set in the PKEY_EN_CFG bit (NVM))

• PKEY_LKP_EN_FSLS: PONKEY Long Key Press Fail-Safe-Lock-Skip bit / EN deasserted Fail-Safe-Lock-Skip bit)

PWRCTRL1 and PWRCTRL2 are digital inputs controlled from an application processor (see PWRCTRL1, PWRCTRL2). They are dedicated to managing different application power modes or special regulator reset features.

PWRCTRL1 and PWRCTRL2 can be independently muxed onto each regulator instance (BUCKx, LDOx or GPOx).

For example, BUCK1 may be controlled by PWRCTRL2, and BUCK2, BUCK2, and LDO5 can be controlled by PWRCTRL1, and so on.

A regulator instance and external command (GPO) can be controlled by a single PWRCTRL signal. For each regulator instance, a PWRCTRL input can be used either to:

• Switch between the xxx_MAIN_CR register or the xxx_ALT_CR register of a regulator (where xxx is the regulator instance)

– The regulator behaves according to the selected xxx_MAIN_CR or xxx_ALT_CR register

• Reset a regulator instance to its default value (from the NVM)

PWRCTRL1 or PWRCTRL2 can be used to suspend the watchdog, typically when the AP is in low-power mode.

Figure 12 PWRCTRLx logic circuitry principle provides the logic circuitry principle showing:

• How a buck converter is controlled by a PWRCTRLx

PWRCTRL1_POL and PWRCTRL2_POL bits set the polarity of PWRCTRL1 and PWRCTRL2 respectively. Those settings are applicable to all regulators and external commands (GPO) (not linked to a single regulator).

PWRCTRLx_POL: polarity of PWRCTRLx signal (with x = 1, 2): 0: active low; 1: active high. See Table 22 PWRCTRLx polarity truth table.

WDG_PWRCTRL_SEL [1:0]: Watchdog control source selection. When PWRCTRLx is active, the watchdog timer is suspended. When PWRCTRLx is inactive, the watchdog timer is running (if watchdog is enabled) (see Turn-OFF condition triggered by a hard fault).

Note: There is one instance of the following registers per regulator instance:

PWRCTRL_SEL [1:0]: BUCKx control/reset source selection.

PWRCTRL_DLY_H [1:0]: BUCKx control/reset source shift delay from low to high level (typically to perform the power ON sequence between different regulators; driven by a PWRCTRL signal). 0 = no delay; 1 = 1.5 ms delay; 2 = 3 ms delay; and 3 = 6 ms delay.

PWRCTRL_DLY_L [1:0]: BUCKx control/reset source shift delay from high to low level (typically to emulate the power OFF sequence between different regulators; driven by a PWRCTRL signal). 0 = no delay; 1 = 1.5 ms delay; 2 = 3 ms delay; and 3 = 6 ms delay.

PWRCTRL_EN: BUCKx control source enable. 0: disable, 1: enable. When enabled, BUCKx is controlled by a PWRCTRL signal:

• If PWRCTRL is inactive, the BUCKx_MAIN_CR register is used to control BUCKx
• If PWRCTRL is active, the BUCKx_ALT_CR register is used to control BUCKx

PWRCTRL_RST: BUCKx independent reset source enable. 0: disable, 1: enable. When enabled, BUCKx is reset by a PWRCTRL signal. See Regulator-independent reset detailed behaviors (PWRCTRL_RST) for details:

1. If PWRCTRL is active
2. BUCKx is disabled (forced by the DISABLEn signal in Figure 15 Reset power-cycle sequence example.)
3. The BUCKx_MAIN_CR and BUCKx_ALT_CR registers are reset to default value (the NVM default value is reloaded in both registers).
4. If PWRCTRL is inactive, the BUCKx_MAIN_CR register is used to control BUCKx.

PWRCTRL delay blocks are independent for each regulator. A delay block allows a PWRCTRLx signal to shift by preprogrammed delays. Each delay block is composed of two parts (a delay high and a delay low). The first operates at a high input level, and the second operates at a low input level.

Delay blocks are typically used to emulate power sequences between regulators when entering or leaving a low-power mode.

The independent reset feature is controlled by a PWRCTRLx input pin (PWRCTRL_SRC [1:0]) and it is enabled by setting the PWRCTRL_RST bit. This feature allows a regulator to reset to its default NVM value from an AP hardware signal “on the fly” (which cannot be done by I²C access).

When the PWRCTRLx input pin is active, regulator xxx is forced into OFF mode. xxx_MAIN_CR and xxx_ALT_CR registers are both reset to default values (the NVM default value is reloaded in both registers from the related NVM shadow register).

When the PWRCTRLx input pin is inactive, regulator xxx is controlled by xxx_MAIN_CR register content.

Figure 14 Regulator-independent reset behavior example provides an example to illustrate regulator-independent reset behaviors using the PWRCTRL2 to control the LDO2 independent reset.

RSTn is a bidirectional reset pin both for the PMIC and the application processor. It has a digital input/open drain output topology with an internal pull-up resistor (RPU).

• When the PMIC asserts RSTn, it drives the RSTn signal low (open drain internal transistor). The application processor is forced into a reset state.
• When the PMIC does not assert RSTn, the RSTn pin is in high impedance and the RSTn signal goes high (due to the pull-up resistor) if the RSTn signal is not asserted low externally (for example by a reset push- button or from an application processor asserting the reset signal low). In that case, the PMIC RSTn pin becomes a digital input and it monitors the RSTn signal.

In the POWER_ON state, the RSTn pin can be driven by the application processor or a reset push-button.

When the application processor asserts RSTn low exceeding the t_RSTnAS duration, it immediately triggers a reset sequence of the PMIC by performing a non-interruptible power cycle:

1. The PMIC asserts RSTn low (forcing the AP to keep it in reset, and in case that the AP releases the reset before the end of the sequence)
2. POWER_DOWN sequence
3. CHECK&LOAD
4. POWER_UP sequence
5. PMIC deasserts RSTn and monitors RSTn
6. PMIC waits for the RSTn signal to go high before entering POWER_ON (to prevent an infinite loop of reset sequences)

The PMIC can detect a negative pulse on RSTn shorter than the tRSTnAS duration. The PMIC must detect a negative pulse longer or equal to the tRSTnAS duration.

From step 2 to step 4 (in the above sequence), LDOs, GPOs and buck regulators follow a POWER_DOWN sequence followed by a POWER_UP sequence as defined in POWER_UP / POWER_DOWN sequence except for regulators with the mask_reset option bit set.

The mask_reset option can be defined for each regulator by setting the corresponding MRST bit in the corresponding BUCKS_MRST_CR or LDOS_MRST_CR or GPOS_MRST_CR registers.

When the mask_reset option is set to a regulator, the MAIN and ALTERNATE related registers are not reset and content is maintained during and after the reset power cycle. Nevertheless, the PWRCTRLx settings are reset for all regulators, including those with the mask_reset option set:

• POWER_DOWN is not performed.
• MAIN and ALTERNATE register values are not reset, and their contents are maintained with the current value
• PWRCTRLx register settings are reset (xxx_PWRCTRL_CR)

The PMIC always ends the power cycle in the POWER_ON state, regardless of the PWRCTRLx value, as all PWRCTRLx settings have been reset during the power cycle.

If RSTn is asserted in MAIN mode, regulators with the mask_reset option set are not impacted at all by the reset sequence, keeping V_OUT, EN, and PREG_MODE unchanged.

If RSTn is asserted in the ALTERNATE mode, V_OUT, EN, and PREG_MODE switch to the content of the [regulator]_MAIN_CR register values when the POWER_DOWN sequence ends before the POWER_UP sequence starts.

Figure 15 Reset power-cycle sequence example. illustrates a reset power cycle of the PMIC.

For RANK_DLY and RST_DLY, see Table 132 NVM_MAIN_CTRL_SHR2.

Settings related to the example in Figure 15 Reset power-cycle sequence example.:

LDO5 with mask_reset option set (LDOS_MRST_CR[LDO2_MRST] = 1) is not impacted by the reset power- cycle.

BUCK1, BUCK2, and LDO4 are powered down and up at their respective ranks defined in the NVM. LDO5 is enabled by I²C. So, it is powered down first and not restarted (as not defined in the NVM to start). Mask_reset is valid once. It is cleared in the CHECK&LOAD state. So, it is cleared following a turn-off condition, a VINPOR, and a RSTn assertion.

When RSTn is released by the application processor, the PMIC keeps RSTn asserted (the RSTn signal stays low), meaning that the application processor is kept in reset until the PMIC releases the RSTn signal.

The PMIC implements a thermal protection to prevent overheating damage. PMIC junction temperature is permanently monitored by an embedded thermal sensor.

The first level of thermal protection consists of an alarm sent by an interrupt to the application processor:

• When T_j rises above the TWRN_Rise threshold, the PMIC generates a THW_RI interrupt
• When T_j falls below the TWRN_Fall threshold, the PMIC generates a THW_FA interrupt

The application processor can decrease the application activity load, in order to decrease the application power consumption. Alternatively, a second level of thermal protection may occur.

The second level of thermal protection consists of triggering a turn-off hard-fault condition:

• When T_j rises above the TSHDN_Rise threshold, the PMIC generates a turn-off hard-fault condition, and the thermal fail-safe counter is incremented (TSHDN_FLT_CNT ++):
  • If the thermal fail-safe counter reaches the maximum number of power cycles defined in the NVM (TSHDN_FLT_CNT > TSHDN_FLT_CNT_MAX), then the PMIC goes into the FAIL_SAFE_LOCK state.
  • Alternatively, when T_j falls below the TSHDN_Fall threshold and a tTSHDN_DLY delay ends, the PMIC restarts.

See Fail-safe management for details about fail-safe counter management.

All regulators implement protection against overcurrent (OC) on their output.

For each regulator, the PMIC embeds 2 levels of protection against overcurrent and short-circuits:

• Level 0 (default): independent regulator OCP Hiccup mode management
• Level 1: PMIC OCP fail-safe management (see Fail-safe management)

The default level of protection is defined in the NVM (NVM_FS_OCP_SHR1/2) for each regulator, and can be changed at runtime by software (FS_OCP_CR1/2).

Each PMIC regulator operates independently in Hiccup mode:

• When a short-circuit or an overcurrent occurs, the output current is limited to ILDOLIM (for LDO) and IBKLIM (for buck).
• If the SC or OC lasts more than t_{OCPDB_LDO} or t_{OCPDB_BUCK} (respectively for LDO or buck):
  • The regulator turns OFF for the t_{HICCUP_DLY} duration
  • An interrupt is generated (if the interrupt is unmasked by software)
• Once the t_{HICCUP_DLY} timer elapses, the regulator turns ON
  • If the SC or OC is removed, the LDO operates normally
  • If the SC or OC stays present, the regulator goes into step 1, repeating the cycle until the overload disappears (hiccup)

Notes:

• 1) When the t_{HICCUP_DLY} timer duration is set to 0, the regulator is turned-OFF (interrupt-generated) and it does not restart (step 3 is skipped).
• 2) The t_{HICCUP_DLY} timer duration can be adjusted in the NVM by setting the HICCUP_DLY [1:0] bit field in the NVM_BUCKS_IOUT_SHR2 shadow register, then programming the NVM.

3) The t_{HICCUP_DLY} timer is reset if a POWER_DOWN occurs at the same time. In this way, the IP can restart with its assigned RANK at the next POWER_UP. This happens even if the mask reset is set and/or t_{HICCUP_DLY} is set to ‘0’.

Each PMIC regulator can be set independently to trigger a hard-fault condition when an overcurrent or a short circuit occurs:

• When a short-circuit or an overcurrent occurs, the output current is limited to ILDOLIM(for LDO) and IBKLIM (for buck).
• If the SC or OC lasts more than tOCPDB_LDO or tOCPDB_BUCK (respectively for LDO or buck), the PMIC generates a turn-off hard-fault condition. OCP_SR1 or OCP_SR2 is updated with the OCP fault source, and the OCP fail-safe counter (1) is incremented (OCP_FLT_CNT ++):
  • If the OCP fail-safe counter reaches the maximum number of power cycles defined in the NVM (OCP_FLT_CNT > OCP_FLT_CNT_MAX), the PMIC goes into FAIL_SAFE_LOCK state.
  • Alternatively, when the tHICCUP_DLY delay ends, the PMIC restarts.

There is a single OCP fail-safe counter (OCP_FLT_CNT) for all regulators. It is incremented each time a regulator triggers a hard-fault regardless of the regulator instance.

The PMIC has an internal watchdog timer. A watchdog timer expiration generates a turn-off hard-fault condition (see Turn-off conditions) followed either by a PMIC restart (power cycling) or by the PMIC going into the FAIL_SAFE_LOCK state.

The watchdog can be enabled/disabled by software or at power-up (NVM settings):

• Software: set/reset WDG_EN bit at runtime
• NVM: set/reset NVM_WDG_EN bit, then program the NVM

As soon as the watchdog is enabled, the software should periodically set the WDG_RST bit (self-cleared) to reload the timer down counter WDG_TMR_CNT [7:0] with the value defined in the WDG_TMR_SET [7:0] bit field.

The software can read the watchdog timer down counter (WDG_TMR_CNT [7:0]) to check the remaining duration before expiration.

A turn-OFF hard-fault condition occurs if the watchdog timer expires. The turn-off condition is followed by a POWER_DOWN sequence either by a PMIC restart (POWER_UP then POWER_ON) or by the PMIC going into the FAIL_SAFE_LOCK state. (See Fail-safe management for details about the behavior following a turn-off hard-fault event).

Enabling the watchdog (from WDG_EN = 0 to 1) to reload the timer down counter (WDG_TMR_CNT [7:0]) with the value defined in the WDG_TMR_SET [7:0] bit field.

When enabled, the watchdog timer remains active in the POWER_ON state.

The watchdog timer can be disabled at runtime by setting WDG_EN = 0. Alternatively, the watchdog timer is automatically disabled when PMIC goes into the OFF state or the FAIL_SAFE_LOCK state (regardless of turn- OFF condition source).

When enabled (WDG_EN = 1), the watchdog timer can be suspended automatically from one PWRCTRLx signal. The WDG_PWRCTRL_SEL [1:0] bit field allows for the selection of the PWRCTRLx source to suspend the watchdog. It is suitable to automatically suspend/freeze the watchdog when the application is in low-power mode:

• When PWRCTRLx is inactive (the application is running), the watchdog timer down counter is running. The software should set the WDG_RST bit periodically to reload the timer down counter.
• When PWRCTRLx is active (the application is in low-power mode), the watchdog timer down counter is suspended (frozen). When PWRCTRLx becomes inactive (the application leaves the low-power mode), the watchdog down counter restarts from the current WDG_TMR_CNT [7:0] value (counter WDG_TMR_CNT [7:0] is not reloaded from WDG_TMR_SET [7:0] value).

The I²C interface works in slave mode. It supports both standard and fast modes with a data rate up to 400 Kb/s. It also supports fast mode plus (FM+) with a data rate up to 1 Mb/s, which is a suitable frequency for DVS operations.

There is an I²C slave address for the STPMIC1L.

The address is stored in the NVM_I²C_ADDR_SHR[6:0] shadow register bit field. The hard-coded I²C default address defined in the NVM is 0x33.

Each transaction is composed of a start condition followed by an 8-bit packet number representing either a device ID plus R/W command, register address, or register data coming to/from the slave.

SeeTable 30 . VERSION_SR. An acknowledgment is needed after each packet. This acknowledgment is given by the receiver of the packet. Transaction examples are given in Table 32 TURN_ON_SR and Table 34 TURN_OFF_SR. Multi-read and multi-write operations aresupported.

The PMIC's built-in non-volatile memory provides high flexibility to support a wide range of applications.

Its write management through I²C allows for the customization of the PMIC directly in final applications during product development and mass production.

The NVM read operation is performed automatically in the INIT&LOAD state and in the CHECK&LOAD state to set control registers with default values and configure the POWER_UP and POWER_DOWN sequence.

The NVM write operation can be performed several times (NVMEND cycles max) during application development debugging procedures. Once the final settings have been defined, these can be written in the NVM content of each part mounted on the customer application that is written in the production line under a controlled environment.

In addition, the PMIC supports the NVM CRC check (or checksum) to guarantee its content integrity. The CRC is computed by the PMIC during an NVM write operation. After the NVM write, the user reads back the NVM content to check that the content is OK (and implicitly that the computed CRC is valid). Then, each time the PMIC reads the NVM (in the INIT&LOAD and in the CHECK&LOAD states) if the CRC is not OK, the PMIC does not start up.

The NVM read operation is fully managed by the PMIC.

For each read operation, the PMIC automatically loads the NVM content into NVM shadow registers. It means that shadow register content is a copy of NVM content.

When the PMIC power supply is connected (VIN > VINPOR_Rise), the PMIC state machine goes into the INIT&LOAD state (see Functional state machine). In this state, an NVM read operation is performed to check if the PMIC can start up automatically, depending on the AUTO_TURN_ON NVM bit value.

If the AUTO_TURN_ON bit is not set, the PMIC goes into the OFF state, or into the CHECK&LOAD state and continues to POWER_UP automatically.

Before each POWER_UP sequence, the NVM read operation is performed in the CHECK&LOAD state. NVM content is loaded into shadow registers and NVM content integrity is checked with CRC. Additionally, the PMIC initializes BUCK and LDO control registers with values predefined in the NVM and it configures the POWER_UP and POWER_DOWN sequence of regulators.

The NVM write operation can be performed by the I²C interface for customization purposes (see max cycles in NVMEND).

The writing procedure can be performed in two ways:

• Customizing a pre-programmed device directly from the application host processor via the I²C interface

Special attention must be given when a new I²C address needs to be programmed.

When a different I²C address is written in NVM_I²C_ADDR_SHR, this new address becomes effective only after a “NVM write operation” after reloading the NVM (INIT&LOAD or CHECK&LOAD state).

If a “NVM write operation” is not performed following the I²C address change in the shadow register, the previously programmed I²C address is loaded from the NVM during the next POWER_UP sequence.

When the PMIC is customized with the LOCK_NVM bit set in the NVM_I²C_ADD_SHR followed by a programing command (NVM_CMD [1:0] = 0b01), then the NVM write operation becomes disabled immediately. Any new programing command execution is ignored and the NVM_WRITE_FAIL bit is set in NVM_SR.

All NVM_xxx bits of shadow registers have related xxx mirror bits in the control registers section allowing the software to override the NVM’s predefined values at runtime. Each time the NVM is reloaded, related xxx mirror bits are also reloaded with the NVM’s predefined values.

All bits specified as reserved in registers with R/W must not be modified.

So, before writing on a register with a reserved bit, the user should read the content of the register and should only modify bits that are not reserved, then write to the register.

• Address: 0x00
• Default: 0x1X (X depends on the PMIC variant)
• Description: PMIC product ID status register.

• Address: 0x01
• Default: 0x11
• Description: PMIC version status register.

• Address: 0x02
• Default: 0b0000x00x where x depends on the turn-on condition
• Description: Stores last condition, which has turned on the PMIC.

From the NO_SUPPLY state, if the AUTO_TURN_ON bit is set in the NVM, the TURN_ON_SR [AUTO] is set.

In the OFF state, the TURN_ON_SR is cleared. When a turn-on condition occurs, the related turn-on bit is set in TURN_ON_SR before leaving the OFF state.

The TURN_ON_SR is cleared in the POWER_DOWN state.

• Address: 0x03
• Default: 0bx0xxxxxx, where x depends on the turn-off condition
• Description: Stores last condition, which turns off the PMIC.

The TURN_OFF_SR register is reset in the POWER_DOWN state. Then TURN_OFF_SR is set either when going into the OFF state or when going into the FAIL_SAFE_LOCK state (see Turn-off conditions and State explanations ).

• Address: 0x04
• Default: 0bxxxxxxxx, where x depends on a power-OFF condition which restarts the PMIC
• Description: Stores last condition, which restarts the PMIC (power cycle).

The RESTART_SR register is reset in the POWER_DOWN state. Then RESTART_SR is set when going into the CHECK&LOAD state (see Turn-off conditions and State explanations).

• Address: 0x05
• Default: 0b000000xx, where x depends on regulator that has triggered the OCP.
• Description: If the PMIC is turned OFF or restarted due to an OCP from regulator, OCP_SR1 or OCP_SR2 store the regulator instance that triggered the OCP.

The OCP_SR1 register is reset in the POWER_DOWN state. If an OCP hard-fault condition occurred, then the OCP_SR1 register is set before leaving the POWER_DOWN state (see Turn-OFF condition triggered by software switch-off and Turn-off conditions and State explanations).

• Address: 0x06
• Default: 0b000xxxx0, where x depends on regulator that has triggered the OCP.
• Description: If the PMIC is turned OFF or is restarted due to an OCP from a regulator, OCP_SR1 or OCP_SR2 store the regulator instance that triggered the OCP.

The OCP_SR2 register is reset in the POWER_DOWN state. If an OCP hard-fault condition occurred, then the OCP_SR2 register is set before leaving the POWER_DOWN state (see Turn-OFF condition triggered by software switch-off and Turn-off conditions and State explanations).

• Address: 0x07
• Default: 0b000000xx, where x depends on regulator status (0 = disabled, 1 = enabled)
• Description: This register reflects the IP current enable status despite the setting in MAIN or ALT configurations.