Risks of ESD

ESD is a serious issue in solid state electronics, such as integrated circuits (ICs). ICs are made from semiconductor materials (such as silicon) and insulating materials (like silicon dioxide): both can suffer permanent damage when subjected to high voltages.

The damaging effects of ESD pose unacceptable risks in many areas of technology, and it is necessary to control such interference and reduce the risks to acceptable levels through;

• Simulation and testing of electronic devices using models
• Definition of standards.

The following sections focus on the ESD protection of STM32 (based on Arm® cores) microcontrollers listed in Table 1.

Several models describe how to simulate an ESD stress. The schematic circuit in the figure below shows how to generate an ESD event to a device under test (DUT). It is the basis of these models.

An ESD simulator with a special output circuit called the human body model (HBM) is often used to test the susceptibility of electronic devices to ESD stress from human contact. This model simulates the discharge that may occur when a human touches an electronic device (either a system or a component).

The HBM consists of a capacitor in series with a resistor (see Figure 1 Electrostatic discharge test (ESD generator and DUT)). The capacitor is charged to a specified voltage from an external source, and then suddenly discharged through the resistor into an electronic terminal of the DUT.

This model simulates what happens when a machine becomes electrostatically charged and subsequently discharges into an electronic device when it comes in contact with it.

The MM test circuit consists of charging up a 200 pF capacitor to a certain voltage and then discharging this capacitor directly into the DUT.

The following subsections provide an overview of the most important ESD standards.

The ESD association and JEDEC solid state technology association have established a joint standard procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility to damage or degradation by exposure to a defined HBM ESD (1.5 kΩ, 100 pF and 8 kV).

The SP723 EIAJ IC121 MM standard ensures that the ESD capability is typically greater than 2 kV (from 200 pF) with no serial resistor. For this standard, R_D and C_D of Figure 1 Electrostatic discharge test (ESD generator and DUT) are respectively 0 Ω and 200 pF.

The IEC61000-4-2 standard for ESD protection is ±15 kV for air and ±8 kV for contact. The typical waveform of the output current of the ESD generator is described in the figure below.

For this standard, R_D and C_D of Figure 1 Electrostatic discharge test (ESD generator and DUT) are respectively 330 Ω and 150 pF. This standard is more accurate for performing tests at system level rather than at electronic device level.

This standard method classifies microcircuits according to their susceptibility to damage or degradation by exposure to ESD. For this standard R_D is 1.5 kΩ and C_D is 100 pF. This standard is well suited for electronic device tests as ESD stress can be applied directly onto the pins.

The application must be aligned with one or more standards as agreed with the customer. Table 2 Test conditions for ESD standards summarizes the test conditions for the ESD standards.

When an ESD event occurs, the standards outlined in Standards overview describe four test results that can occur in a real application.

The test results are as follows:

• normal performance continues within the specification limits
• temporary degradation or loss of function or performance that is self-recoverable
• temporary degradation or loss of function or performance which requires operator intervention or system reset (the operator can be the end user)
• degradation or loss of function that is not recoverable due to damage of equipment (components) or software, or loss of data

The risk of failure is the same for touch sensing application as for other applications. When a touch occurs, the system or equipment can fail if it is not sufficiently robust.