AN5342 · Application noteHow to use error correction code (ECC) management for internal memories protection on STM32 MCUs
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Conclusion

Conclusion

With a higher level of integration of the microelectronics in a system, memory cells are more prone to failure, hence ECC memory integrity protection becomes more important. The main difference between the RAM ECC compared to a regular peripheral is that the RAM ECC cannot be turned off as it is an integral part of the RAM interface.

This application note is a description of the ECC in RAM, flash memory and cache memory.

It provides also procedures to deal with ECC errors in RAM and flash memory.

ECC sequences

For ECC testing in flash memory, the following sequences that lead to SEC and DED errors for different flash memory word lengths can be used.

128-bit sets:

  1. Select a flash page.
  2. Erase the page.
  3. Choose an address AD#1 on the page.
  4. Perform a 128-bit write on AD#1 with data: 0x00000000 00000000 00000000 0000000A
  5. Perform a 128-bit write on AD#1 with data: 0x00000000 00000000 00000000 0000000C
    Note:

    This is correct, writing twice on the same address is performed on purpose.

  6. Read data from AD#1 (128‑bit read) and check ECC flags related to error detection/correction. Data read should be 0x00000000 00000000 00000000 0000000A and one error correction on this address must be reported.
  7. Choose an address AD#2 on the page (AD#1 <> AD#2).
  8. Perform a 128-bit write on AD#2 with data: 0x00000000 00000000 00000000 00000000
  9. Perform a 128-bit write on AD#2 with data: 0x00000000 00000000 00000000 00000004
    Note:

    This is correct, writing twice on the same address is performed on purpose.

  10. Read data from AD#2 (128‑bit read) and check ECC flags related to error detection/correction. Data read should be 0x00000000 00000000 00000000 00000000 and one error correction on this address must be reported.
  11. Choose an address AD#2 on the page (AD#1 != AD#2 != AD#3).
  12. Perform a 128-bit write on AD#3 with data: 0x00000000 00000000 00000000 0000000A
  13. Perform a 128-bit write on AD#3 with data: 0x00000000 00000000 00000000 0000000C
    Note:

    This is correct, writing twice on the same address is performed on purpose.

  14. Perform a 128-bit write on AD#3 with data: 0x00000000 00000000 00000000 00000004
    Note:

    This is correct, writing three times on the same address is performed on purpose.

  15. Read data from AD#3 (128‑bit read) and check ECC flags related to error detection/correction. Two error detections on this address must be reported.

256-bit sets:

  1. Select a flash page.
  2. Erase the page.
  3. Choose an address AD#1 on the page.
  4. Perform a 256-bit write on AD#1 with data: 0xCCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCC1
  5. Perform a 256-bit write on AD#1 with data: 0xCCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCC0
    Note:

    This is correct, writing twice on the same address is performed on purpose.

  6. Read data from AD#1 and check ECC flags related to error detection/correction. Data read should be 0xCCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCC1 and one error correction on this address must be reported.
  7. Choose an address AD#2 on the page (AD#1 <> AD#2).
  8. Perform a 256-bit write on AD#2 with data: 0xCCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCB
  9. Perform a 256-bit write on AD#2 with data 0xCCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
    Note:

    This is correct, writing twice on the same address is performed on purpose.

  10. Read data from AD#2 and check ECC flags related to error detection/correction. Two error detections on this address must be reported.
Note:

In addition to the patterns published here, there are many different effective combinations. In particular, DED is relatively simple to achieve because most rewrites tend to produce multiple bit errors.

Revision history

Table 7. Document revision history
DateVersionChanges
27-May-20191Initial release.
6-Jan-20202Updated:
  • Section Introduction
  • Section 2.2 RAM ECC
  • Section 2.3 Flash memory ECC
31-Mar-20223Updated:
  • Section Introduction
  • Section 2 ECC overview
  • Section 2.2 RAM ECC
  • Section 2.3 Flash memory ECC
  • Added Section 3.1.3 Interpreting FAR (failing address register)
21-Feb-20234Updated document to cover STM32H5, STM32H7, and STM32U5 series microcontrollers.
  • Section Introduction
  • Section General Information
  • Section 2 ECC overview
  • Section 2.1 ECC implications
  • Section 2.2 RAM ECC
  • Section 2.3 Flash memory ECC
  • Section 2.4 Cache memory ECC
  • Section 3.1.2 ECC ISR
  • Section 3.2.1 Flash memory ECC ISR

Added:

  • Section 2.5 ECC testing
10-Jul-20235Updated:
7-Feb-20246Updated:
11-Jun-20257Updated:
24-Feb-20268Updated:
Added: