| STLC4550 - WIFI solution for mobile solution for mobile phones and portable devices |
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| Datasheet |
| Reference |
Filesize |
Pages |
Last Updated |
| STLC4550 |
143KB |
5 |
07/02/2006 |
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| Orderable Products |
| Device |
Status |
RoHS |
Package |
Purchase |
| STLC4550 |
Preview |
Ongoing |
LFBGA 8.5x8x1.4 240 F16x15 0.5 |
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| Features and Description |
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Extremely small footprint |
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Ultra Low Power consumption |
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Fully compliant with the IEEE 802.11b and
802.11g WLAN standards |
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Support for 54, 48, 36, 24, 18, 12, 9, and
6Mbps OFDM, 11 and 5.5Mbps CCK and
legacy 2 and 1Mbps data rates |
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Single Chip 802.11b/g WLAN solution with fully integrated:
- - Zero IF (ZIF) transceiver
- - Voltage Controlled Oscillator (VCO)
- - High-speed A/D and D/A converters
- - Radio Power Management Unit (PMU)
- - OFDM and CCK baseband processor
- - ARM9 Media Access Controller (MAC)
- - SPI serial host interface
- - SDIO (4-bit) serial host interface
- - Passive components integration
- - PA bias control
- - Flexible integrated Power ManagementUnit
- - Glueless FEM interface
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Intelligent Power Control, Including 802.11
Power Save Mode |
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Fully integrated Bluetooth coexistence |
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The STLC4550 is a single chip 802.11b/g WLAN
radio for embedded, low-power and very small
form factor mobile applications. The product
conforms to the IEEE 802.11b and 802.11g
protocols operating in the 2.45GHz ISM
frequency band supporting OFDM data rates of
54, 48, 36, 24, 18, 12, 9, and 6Mbps as well as CCK data rates of 11 and 5.5Mbps and legacy
data rates of 2 and 1Mbps.
The STLC4550 is a fully integrated wireless radio
including a ZIF transceiver, RDocRev1F
Synthesizer/VCO, high-speed data converters, an
OFDM/CCK digital baseband processor, an
ARM9-based MAC and a complete Power
Management Unit with integrated PA bias control.
In addition some passive components are
integrated further reducing the overall reference
design cost and size. An external FEM completes
a highly integrated chip set solution.
Host control is provided by a flexible SPI or SDIO
serial interface. The SPI interface supports a
maximum clock rate of 48MHz whereas the SDIO
supports a maximum clock rate of xxMHz. For
maximum flexibility, the STLC4550 accepts
system reference clock frequencies of 19.2, 26,
38.4 and 40MHz. A reference design evaluation
platform of hardware and software is provided to
system integrators to rapidly enable wireless
connectivity to mobile platforms. |
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| Technical Documents (PDF Files) |
| Data Brief |
| Reference |
Filesize |
Pages |
Last Updated |
| STLC4550 |
143KB |
5 |
07/02/2006 |
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