Customization Process
Through External FPGA

Each customizable device of SPEAr® family is predefined for an easy link with an external FPGA to emulate the eASIC®/Lightspeed® gates. In that way customers can map their logic in the FPGA, interacting with all SPEAr’s IPs and under real constraints.

During project development, the eASIC/Lightspeed logic is isolated and the external FPGA emulates the eASIC/Lightspeed gates.