SPEAR-09-B042

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Reference	File size	Pages	Last Updated
SPEAR-09-B042	917 KB	66	26/05/2008

Device	Status	RoHS	Purchase
SPEAR-09-B042	Preview	Converted

	ARM926EJ-S core @ 333 MHz
	300 kgates reconfigurable logic array with 102 dedicated general-purpose I/Os and 64 Kbytes + 8 Kbytes of configurable internal memory
	Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz
	32-Kbyte ROM, 8-Kbyte common static RAM
	High-performance DMA (8 channels)
	External DRAM memory interface: - 8/16-bit (LPDDR @ 166 MHz) - 8/16-bit (DDR2 @ 333 MHz) - 2 banks available
	Flash interface: - SPI serial (up to 50 Mbit/s)
	SPI master/slave up to 50 Mbit/s: - Compliant with Motorola, Texas Instruments and National Semiconductor
	Large set of connectivity IPs: - Ethernet MAC 10/100 with MII protocol - 2 fully independent USB 2.0 hosts and one USB 2.0 device with embedded PHY - I²C master/slave mode – high, fast and slow speed - UARTs (up to 460.8 Kbit/s) - IrDA (FIR/MIR/SIR) compliant serial link from 9.6 Kbit/s to 4 Mbit/s speed-rate
	ADC 10-bit, 1 MSPS, 8 inputs
	JPEG codec accelerator
	Cryptographic coprocessor (C3) DES/3DES/AES/SHA1
	Dynamic power saving features
	Low power consumption technology

The SPEAr BASIC combines SPEAr family concepts with 65 nm process technology to obtain improved performance and power-reduction features in new SPEAr devices.
ST’s newest configurable SoC integrates an advanced ARM926EJ-S processor core with two16-Kbyte memory caches, running at 333 MHz, for data and instructions and up to 300,000 gates (ASIC-equivalent) of embedded configurable logic.
An extensive set of proven IPs combined with a configurable logic block allows very fast customization of unique and proprietary solutions.
A default customization is offered for customer convenience and for evaluation of available ST IPs.

Customers can evaluate the following:
- Flexible static memory controller
            - NAND/NOR 8/16 bits and SRAM
- LCD controller for TFT/STN panels
            - up to 1024 x 768, 24 bits per pixel
- 9 x 9 keyboard controller
- SD/MMC card interface
- ITU-601 camera interface supporting external and embedded sync
- TDM master/slave
            - 1024 TDM channels with switching capability
- Up to 16 channels bufferized (30 ms) for VoIP
- I²S compliant
- Glueless management of up to 8 SLICs/codecs
- Up to 8 I²C/SPI extensions
- 1-bit DAC (order 2 noise shaper)
- Up to 18 GPIOs, 8 with interrupt capability