Geneva / 22 Feb 2017
With rich on-board features including MEMS microphones and sensors, an audio codec, and a display for user-interface development, the STM32 Discovery kits are ready to support creative demonstrations. Building on the high performance of the STM32F7, the new STM32F723E-DISCO heralds the next generation in flexibility by enabling developers to leverage a richer pool of modules from third-party vendors to further expand functionality. In addition to Arduino™ Uno pin headers, it features a Pmod™ connector from Digilent and a newly defined STMod+™ connector that lets users connect through a provided fan-out add-on board to a Wi-Fi module, SeedStudio Grove modules, MikroElektronika click boards™, or to a breadboard for quick prototyping.
In addition, the Discovery board has a High-Speed USB connector to take advantage of the USB-HS (High-Speed) Device physical layer (PHY) integrated in the STM32F723IEK6 MCU, as well as USB-FS (Full-Speed) connector and a TFT 240x240-pixel LCD touchscreen. There are also preloaded demonstrations, including a WAV audio player, a simple video player, and a voice recorder.
ST has also introduced the NUCLEO-F722ZE board, which is ideal for prototyping and community use. As a STM32 Nucleo-144 board, it contains a 144-pin STM32F722ZET6 MCU featuring 512 Kbytes of Flash memory. It has an ST Zio connector that supports Arduino™ Uno V3 connectivity, as well as an ST morpho extension pin header giving access to all the MCU I/Os.
Support for ST-LINK/V2-1 simplifies programming and debugging without a separate probe. The board comes with the STM32 Cube Hardware Abstraction Library (HAL) and software examples.
Both boards are available immediately from distributors or from the ST website, priced $39 for the STM32F723E-DISCO and $19 for the NUCLEO-F722ZE.
For further information please visit www.st.com/stm32f7 The STM32F722/723 are very-high-performance MCUs featuring 1082-CoreMark/462-DMIPS ARM® Cortex®-M7 core, high DSP performance, advanced peripherals, high-speed off-chip memory transactions, and smart architecture that offloads basic tasks from the CPU for maximum utilization