Technical note

STDES-BCBIDIR test report

Rev 2 - August 2025

Introduction

The STDES-BCBIDIR is an 11 kW bidirectional battery charger that provides a comprehensive solution for high-voltage charging applications in both industrial and automotive fields.

It features two power stages: a power factor correction (PFC) stage and an isolated DC-DC stage.

The PFC stage employs a three-phase full-bridge topology, while the DC-DC stage can be configured with two topologies by externally connecting the resonant cell. Both stages utilize ACEPACK DMT-32 SiC power modules.

The system is controlled by two dedicated control boards, one for the PFC stage and another for the DC-DC stage, each based on the STM32G4 microcontroller.

The PFC stage operates at a switching frequency of 70 kHz. The DC-DC stage operates at a fixed switching frequency of 100 kHz in dual active bridge (DAB) topology or a variable switching frequency ranging from 82 to 235 kHz in CLLC topology. This design achieves a peak system efficiency exceeding 96%.

The STDES-BCBIDIR has a single 11 kW magnetic component, which includes the high-frequency isolation transformer and resonant elements for the CLLC tank, or the isolation transformer and leakage inductance for the DAB topology.

The modular hardware architecture consists of the following components:

Main power board equipped with: ACEPACK DMT-32 SiC power modules, featuring a sixpack topology (M1P45M12W2-1LA) for the PFC stage, and two full-bridge modules (M1F45M12W2-1LA) for the DC-DC stage. The board also includes bulk capacitors, sensing circuits, and an auxiliary power supply.
Driver board: designed for the full-bridge and sixpack ACEPACK DMT-32 SiC power modules, it incorporates the STGAP2SiCD galvanically isolated 4 A dual gate driver optimized for SiC MOSFETs.
Control board: based on the STM32G4 microcontroller series, this board features connectors for communication and programming, test points, and status indicators to facilitate testing and monitoring.

Figure 1. STDES-BCBIDIR reference design

Overview

Features

Reference design modular kit consisting of:
- Main power board - STDES-BCBIDIRP
- Driver board (three for PFC stage, four for DC-DC stage) - STDES-GAP2SICD
- STM32G474RET3 control board (one for PFC stage, one for DC-DC stage) - STDES-BCBIDIRC
PFC stage: 3-phase, 2-level bidirectional AC-DC power converter
- Rated nominal AC voltage: 400 V_AC at 50 Hz
- Rated nominal DC voltage: 800 V_DC
- Nominal power: 11 kW
- Switching frequency: 70 kHz
- Rectifier mode:
  - Power factor: PF >0.99
  - Total harmonic distortion: THDi <5%
  - Inrush current control and soft startup
- Inverter mode:
  - Active and reactive power control
  - Integrated grid connection solution
DC-DC stage: dual active bridge (DAB)/CLLC power converter
- Nominal input voltage 800 V
- Nominal output voltage 550 V to 800 V
- Nominal power 11 kW
- DAB: switching frequency 100 kHz
- CLLC: switching frequency range 82 to 235 kHz
System key features
- ACEPACK DMT-32 power module for high integration level
- High frequency operation for weight and size reduction
- Bidirectional capabilities
- DAB soft switching behavior enabled by enhanced modulation management techniques.
- Peak efficiency: greater than 96%

Specifications

Table 1. Main characteristics
Description	Symbol	Min.	Typ.	Max.	Unit	Comment
Three-phase input voltage	V_AC	208		400	V	Line to line voltage
Output voltage	V_DC	550	800	850	V
Maximum output power	P_OUTmax		11		kW	At nominal voltages
AC line frequency	f_g		50		Hz
Power factor	PF		0.9	0.996	-
Total harmonic distortion	THD_i		<5		%	At overall conditions
Switching frequency PFC stage	f_sw		70		kHz
Switching frequency DAB	f_sw		100		kHz
Switching frequency CLLC	f_sw	82		235	kHz

HFT connection to STDES-BCBIDIR

The high-frequency transformer (HFT) plus leakage inductor is crucial for the dual active bridge (DAB) topology as it enables efficient energy transfer with reduced losses and compact size.

The correct connection of the primary and secondary windings of the transformer to the power board is essential to ensure the optimal functioning of the board.

The connection of the transformer to the board is made through the connectors: J21, J22, J23, J24. Figure 2 HFT - 2446.0001 AQ magnetic cable labeling shows the electrical diagram of the transformer, and the various cables of the transformer are also shown. Figure 3 HFT - 2446.0001 AQ magnetic connection to the board shows the connection of the transformer to the power board.

The correct connection of the transformer cables to the power board is as follows:

1 (red-marked cable) must be connected to the J21 connector of the STDES-BCBIDIRP
4 must be connected to the J22 connector of the STDES-BCBIDIRP
5 (red-marked cable) must be connected to the J23 connector of the STDES-BCBIDIRP
6 must be connected to the J24 connector of the STDES-BCBIDIRP

Figure 3. HFT - 2446.0001 AQ magnetic connection to the board

Test setup

Safety precautions

Attention: The STDES-BCBIDIR is designed for demonstration purposes only and is not intended for domestic or industrial installations.

DANGER: The high voltage levels used to operate the STDES-BCBIDIR could provoke a serious electrical shock. This reference design must be used in a suitable laboratory by qualified personnel only, familiar with the installation, use, and maintenance of power electrical systems. During operation, do not touch the board as some of its components could reach a very high temperature.

Preliminary test procedure

The preliminary test procedure includes a set of checks needed to verify the proper functionality of key sections: grid relays, sensing section on AC side and DC side, PLL routine, gate-source voltages, PFC (start-up), DAB (start-up). Successfully passing the aforementioned tests allows the board to operate at full load.

By powering the board with the auxiliary voltages (12 V, 7 V) the sensing sections and the relays can be checked

Equipment needed:

Programmable bidirectional AC source
Bidirectional DC electronic load
Low-power multichannel DC source
High-definition multichannel oscilloscope + probes
High precision power analyzer

Grid relay

Grid relays test

To manage the grid connection the STDES-BCBIDIR presents four relays: three of them used for the three-phase connection and one for the neutral. Figure 5 Grid relays management show the section related to the command of the grid relays with a focus on the selectors.

The selector highlighted allows the user the possibility of managing the control of the relays using the MCU or manually. The two configurations of the relays are allowed by the following jumpers connections:

Figure 6. Grid relay jumper configuration

Table 2. Hardware and software requirements
Hardware	Software
STDES-BCBIDIRP	/
Multichannel DC power supply (12 V, 7 V)

Procedure to perform test

Connect the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards V_ext to configure the external auxiliary power supply mode
Connect the jumpers to enable manual control of the relays in the CLOSED position (J39-J40-J41-J42 position 2-3, J35-J36-J37-J38 position 1-2). (Grid relays test, third configuration)
Enable the auxiliary power supply output. Once the auxiliary system is powered with the indicated jumper configuration, the LEDs D8, D9, D10, and D11 will light up (Figure 7 Grid relay check)

Figure 7. Grid relay check

The test allows verifying that the network relays are properly powered.

Sensing section test

To verify correct operation of the voltage and current sensing, the voltage values on the test points shown in the following figures can be verified. The expected voltage values in specific test conditions are shown in the following figures.

Table 3. Hardware and software requirements
Hardware	Software
STDES-BCBIDIRP	-
Multichannel DC power supply	-
Multimeter	-
Oscilloscope	-
AC power supply	-
DC power supply	-

Table 4. Hardware and software configurations
Hardware	Status
DC auxiliary power supply (12 V, 7 V)	Connected

At each sensor, there are three test points: GND, the sensor BIAS, and the conditioned voltage that is sent to the MCU. The voltage values read at these test points, when the system is not powered (with only the auxiliary power enabled), must match the values indicated in PFC section–Grid voltage sensing, PFC section–Grid current sensing, PFC section – Line voltage sensing, PFC section–Line current sensing, DC-DC section–DC voltage sensing and DC-DC section–DC current sensing.

AC sensing

Figure 8. PFC section - Grid voltage sensing

Figure 9. PFC section - Grid current sensing

Figure 10. PFC section - Line voltage sensing

Figure 11. PFC section - Line current sensing

DC sensing

Figure 12. DC-DC section - DC voltage sensing

Figure 13. DC-DC section - DC current sensing

Procedure to perform test

Connect the jumpers to enable manual control of the relays in the OPEN position (J39-J40-J41-J42 position 2-3, J35-J36-J37-J38 position 2-3) (Fig.6, second configuration)
Connect the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards V_ext to configure the external auxiliary power supply mode
Enable the auxiliary power supply output
Check that the voltages read on the test points match the values indicated in Figures 8 to 13 under the conditions respectively @V_ac=0V, @I_ac=0A, @V_dc=0V, and @I_dc=0A
Connect the AC power supply (J15 → PHA, J17 → PHB, J18 → PHC, J27 → N)
Connect a differential probe between J15 (PHA) and J27 (N) and a passive probe between TP58 (Vg_A) and TP55 (GND)
Set an AC voltage of 110 Vrms and enable an AC power supply
Check that the V_(s pk-pk)=G∙ V_(g pk-pk) =0,0044∙319,2=1,40 V (Measurement of the mains voltage and reading of the corresponding sensor)

Figure 14. Measurement of the mains voltage and reading of the corresponding sensor
Disconnect the AC power supply
Connect of the DC power supply (J20 → +, J25 → -)
Connect a differential probe between J20 (+) and J25 (-) and a passive probe between TP41 (Vbus) and TP39 (GND)
Set a DC voltage of 200 Vdc and enable a DC power supply
Check that the V_(s DC)=G∙ V_BUS =0,00343∙201,98=0,692 V (Figure 15)

DANGER: Ensure that the voltage present on connectors J20 and J25 has dropped to zero before touching the connectors

Figure 15. Measurement of the BUS voltage and reading of the corresponding sensor

PLL testing procedure

To test the proper functionality of the phase-locked loop (PLL), a comprehensive test environment and a series of steps must be followed.

The following outlines the necessary environment setup and the detailed steps for conducting the PLL test.

Table 5. Hardware and software requirements
Hardware	Software
STDES-BCBIDIR	STM32CubeIDE
STDES-PFCBIDIRC x3	STSW-BCBIDIR
STDES-PFCBIDIRC
Multichannel DC power supply
8 channel oscilloscope
AC power supply
ST-LINK/V2-ISOL + JTAG

Table 6. Hardware configurations
Hardware	Status
AC input voltage	Connected
DC load	Disconnected
DC auxiliary power supply (12 V, 7 V)	Connected

Table 7. Software configurations
Software	Status
DPC_PWM_INIT	PWM_Safe
DPC_TTC_MODE_INIT	AC2DC_PFC_OPERATION
DAC_CH1_INIT	13
DAC_CH2_INIT	7
DAC_CH3_INIT	8
DAC_G_CH1_INIT	2048
DAC_G_CH2_INIT	2048
DAC_G_CH3_INIT	2048
DAC_B_CH1_INIT	2048
DAC_B_CH2_INIT	2048
DAC_B_CH3_INIT	2048

Procedure to perform test

Connect the jumpers to enable manual control of the relays in the OPEN position (J39-J40-J41-J42 position 2-3, J35-J36-J37-J38 position 2-3). (Fig.6, second configuration)
Connect the STDES-PFCBIDIRC at the connector J1
Connect the AC power supply (J15 → PHA, J17 → PHB, J18 → PHC, J27 → N). Connection of the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards Vext to configure the external auxiliary power supply mode
Connect the three differential probes (PHA-N/PHB-N/PHC-N) and three non isolated probes in the control board (DAC1-GND, DAC2-GND, DAC3-GND)(T29–TP31, T32–TP31, T33–TP31)
Enable auxiliary power supply
Open the firmware: STSW-BCBIDIR_PFC inside the STSW-BCBIDIR and, in the file project DPC_Application_Conf.h set:

#define DPC_TTC_MODE_INIT AC2DC_PFC_OPERATION

#define DPC_PWM_INIT PWM_Safe

#define DAC_CH1_INIT 13

#define DAC_CH2_INIT 7

#define DAC_CH3_INIT 8

#define DAC_G_CH1_INIT 2048

#define DAC_G_CH2_INIT 2048

#define DAC_G_CH3_INIT 2048

#define DAC_B_CH1_INIT 2048

#define DAC_B_CH2_INIT 2048
#define DAC_B_CH3_INIT 2048
Connect the STLINK to the control board of PFC (STDES-PFCBIDIRC on connector J1) section as is shown in Figure 16 and flash the code
Power the board by supplying three-phase voltages (for instance 30 Vrms)

Figure 16. ST-LINK/V2 connected to the control board

The oscilloscope displays the three sinusoidal grid voltages and the theta angle which will appear as a sawtooth synchronized with the sinusoid relating to phase A. Furthermore, it is possible to see the d and q axis components of the voltage. When the steady state condition is reached, the d axis has a positive value while the q axis will be zero how is is shown in PLL test waveforms.

Figure 17. PLL test waveforms

Figure 18. PLL test environment and procedure

Gate-source voltages testing

This test allows to check if the driving signals of the switches are correct sent from the MCU to the driver board.

At the same time, it is possible to verify the correct behavior of the gate driver, and the driver boards in general.

To perform this test a multichannel DC source is needed to provide the auxiliary power supply to the power board

Table 8. Hardware and software requirements
Hardware	Software
STDES-BCBIDIRP	STM32 CUBE IDE
STDES-GAP2SICD x3	FW: STSW-BCBIDIR
STDES-PFCBIDIRC
Multi-channel DC Power supply (12 V, 7 V)
8 channel oscilloscope
ST-linkV2 isol + JTAG

Procedure to perform test (PFC side)

Connect the jumpers to enable manual control of the relays in the OPEN position (J39-J40-J41-J42 position 2-3, J35-J36-J37-J38 position 2-3). (Fig.6, second configuration)
Connect the isolated voltage probes to the VGS of the devices
Connect the STDES-PFCBIDIRC at the connector J1
Connect the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards V_ext to configure the external auxiliary power supply mode
Power the auxiliary section of the board by providing both 12 V and 7 V
Open the FW: STSW_BCBIDIR_PFC inside the STSW-BCBIDIR and verify that in the file project DPC_Application.c when PC_State==FSM_Debug only the following functions must be present:

DPC_MISC_Relay_Cntl(RELAY_GRID_ABC, RELAY_OFF);

DPC_ACT_OutEnable( &tDPC_PWM );

DPC_ACT_Send_Duty_SPWM( &tDPC_PWM,0.0f, 0.0f, 0.0f );

In the file project DPC_Application_Conf.h:

macroDPC_PC_State_Initmust be set to FSM_Debug.

macro DPC_PWM_INIT must be set to PWM_Armed.
Connect the ST-link to the control board of the PFC (STDES-PFCBIDIRC on connector J1) stage as is shown in Figure 16 and flash the code.

Figure 19. Testing procedure of gate to source voltages

By setting an appropriate time base on the oscilloscope, considering a switching frequency of 70 kHz, square waves with a voltage range of +20 to -5 V and a duty cycle of 50% will be displayed, as shown in fig 20.

Figure 20. Gate to source voltage PFC stage

Procedure to perform test (DC-DC side)

Connect the isolated voltage probes to the VGS of the devices.
Connect the STDES-PFCBIDIRC at the connector P1
Connect the low voltage auxiliary power supply (12 V, 7 V ) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards V_ext to configure the external auxiliary power supply mode
Power the auxiliary section of the board by providing both 12 V and 7 V
Open FW: STSW_BCBIDIR_DAB inside the STSW-BCBIDIR, and verify that in the file project DPC_Application.c in case PC_State==FSM_Debug only the following functions must be present:

DPC_ACT_OutEnable(&DAB.tDPC_PWM);

In the file project DPC_Application_Conf.h:

#defineDPC_PC_State_Init FSM_Debug
#define DPC_DAB_PWM_INIT PWM_Armed
Connect the ST-link to the control board of the DAB (STDES-PFCBIDIRC on connector P1) stage as is shown in Figure 16 and flash the code

By setting an appropriate time base on the oscilloscope, considering a switching frequency of 100 kHz, square waves with a voltage range of +20V to -5V and a duty cycle of 50% will be displayed, as shown in Figure 21.

Figure 21. Gate to source voltage DC-DC stage

PFC startup

Subsequently, the load can be increased until the target conditions of the converter are reached.

Table 9. Hardware and software requirements
Hardware	Software
STDES-BCBIDIRP	STM32 CUBE IDE
STDES-GAP2SICD x 3	FW: STSW-BCBIDIR
STDES-PFCBIDIRC x 1
Multichannel DC power supply (12 V, 7 V)
8 channel oscilloscope
ST-LINK/V2-ISOL + JTAG
AC power supply
DC load

Procedure to perform test

Connect the jumpers to enable MCU control of the relays (J39-J40-J41-J42 position 1-2, J35-J36-J37-J38 not connected). (Fig.6, first configuration)
Connect the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards V_ext to configure the external auxiliary power supply mode
Connect the AC power supply (J15 → PHA, J17 → PHB, J18 → PHC, J27 → N) without activation “output disabled”
Connect the three differential voltage probes (PHA-N/PHB-N/PHC-N) and three current probes on the PHA, PHB, and PHC. Connect an additional isolated voltage probe on the DC bus J20-J25
Connect the fan cables to U11 respecting the correct polarity. Connect a 12V power supply to the U10 and provide the power. Move selector J8 in position 2-3 (PFC_FAN)
Connect the DC-Load taking care of the correct polarity at the connector. Positive cable to J20, negative cable to J25, the load must be set to Constant Current mode (CC) and must be disabled
Open the firmware: STSW_BCBIDIR_PFC inside the STSW-BCBIDIR, and verify that in the file project DPC_Application_Conf.h:

///DPC finite state machine DEFINE of STDES-BCBIDIR

#define DPC_PC_State_Init FSM_Idle

#define DPC_PWM_INIT PWM_Armed

#define DPC_TTC_MODE_INIT AC2DC_PFC_OPERATION

#define DPC_CTRL_INIT VOLTAGE_LOOP

///AC MAIN DEFINE of STDES-BCBIDIR

#define DPC_TTC_VAC_EU

///AC MAIN connection DEFINE of STDES-BCBIDIR

#define DPC_AC_3W

///DC OUTPUT DEFINE of STDES-BCBIDIR

#define DPC_PFC_VDC_OUT 800

#define DPC_PFC_VDC_rampstart 760

///PROTECTION

//AC-DC

#define DPC_PFC_VAC_RMS_OVP 250

#define DPC_PFC_VAC_RMS_UVLOP 10

#define DPC_PFC_VAC_RMS_UVP 7

#define DPC_PFC_IAC_OCP 7

#define DPC_PFC_VDC_OVP 850

#define DPC_PFC_IDC_OCP 7
Connect the STLINK to the control board of the PFC (STDES-PFCBIDIRC on connector J1) stage as is shown in Figure 16 and flash the code
Enable three-phase power supply (230 Vrms)
After powering the board (230 Vrms), setting a time base of 1 second, and appropriately adjusting the zoom, waveforms like those in figure 22 will be displayed on the oscilloscope

Shutdown:
- Gradually reduce the load to zero
- Disconnect the AC power supply
- Enable the load to discharge the capacitors of the BUS
DANGER: After performing the test and disconnecting the AC power supply, it is necessary to re-enable the load to discharge the output BUS capacitors. Furthermore, before touching connectors J20, J25 ensure with a multimeter that there is no residual charge on the DC BUS capacitors.

Figure 22. Start-up waveforms of the PFC

DAB startup

This test is used to verify the DAB functionalities up to full load. By following the procedure outlined below, the converter executes the startup phase, bringing the DAB stage to nominal voltage conditions.

Subsequently, the load can be increased until the target conditions of the converter are reached.

Table 10. Hardware and software requirements
Hardware	Software
STDES-BCBIDIRP	STM32CubeIDE
STDES-GAP2SICD x 4	FW: STSW-BCBIDIR
STDES-PFCBIDIRC x 1
Multichannel DC power supply
8 channel oscilloscope
ST-LINK/V2-ISOL + JTAG

Table 11. Hardware configurations
Hardware	Status
AC input voltage	Connected
DC load	Connected
DC auxiliary power supply (12 V, 7 V)	Connected

Table 12. Software configurations
Software	Status
DPC_PWM_INIT	PWM_Armed

Procedure to perform test

Connect the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J19, J10) towards Vext to configure the external auxiliary power supply mode
Connect the transformer according to the instruction in chapter 3
Connect the DC-Source taking care of the correct polarity at the connector. Positive cable to J20, negative cable to J25
Connect the DC-Load taking care of the correct polarity at the connector. Positive cable to J28, negative cable to J29, the load must be set to Constant Current mode (CC) and must be disabled
Connect the fan cables to U11 respecting the correct polarity. Connect a 12 V power supply to the U10 and provide the power. Move selector J8 in position 1-2 (DCDC_FAN)
Connect the four differential voltage probs: OUTA_DAB1- OUTB_DAB1 (TP94-TP95), OUTA_DAB2- OUTB_DAB2 (TP96-TP97) VBUS (TP92-TP84), VLOAD (TP126-TP127). Connect three hall-effect current probe on IBUS (cable connected to J59), ILOAD (cable connected to J20), IDAB1(cable connected to J28)
Open the firmware: STSW_BCBIDIR_DAB inside the STSW-BCBIDIR, and verify that in the file project DPC_Application_Conf.h::

/// DPC finite state machine DEFINE of STDES_DABBIDIR

#define DPC_DAB_ADPPWM

#define DPC_PC_State_Init FSM_Idle

#define DPC_FSM_RUN_INIT Run_Idle

#define DPC_FSM_STATE_INIT DPC_FSM_WAIT

#define DPC_CTRL_INIT DAB_VOLTAGE_LOOP

#define DPC_DAB_PWM_INIT PWM_Armed

#define DPC_DAB_MODE_INIT HV2LV

///DC OUTPUT DEFINE of STDES-DCDC_DAB

#define DPC_DAB_VDC_OUT 800

#define DPC_DAB_IDC_OUT 5

///PROTECTION HV2LV

#define DPC_DAB_VDCHV_OVP 850

#define DPC_DAB_VDCHV_UV 650

#define DPC_DAB_VDCHV_UVLO 30

#define DPC_DAB_VDCHV_MIN 20

#define DPC_DAB_IDCHV_OCP 5

#define DPC_DAB_IDCLV_OCP 5

#define DPC_DAB_VDCLV_OVP 900
Connect the ST-LINK to the control board of the DAB (STDES-BCBIDIRC on connector P1) stage as is shown in Figure 16 and flash the code
Enable DC power supply (800 VDC)
Results

After powering the board (800 VDC), setting a time base of 1 second, and appropriately adjusting the zoom, waveforms like those in figure 23 will be displayed on the oscilloscope
Shutdown:
- Gradually reduce the load to zero
- Disconnect the DC power supply
- Re-enable the load to discharge the capacitors of the output BUS
- Discharge the DC BUS if there is a residual voltage, with a suitable discharge circuit
DANGER: After performing the test and disconnecting the DC power supply, it is necessary to re-enable the load to discharge the output BUS capacitors. Furthermore, before touching connectors J20, J25, and J28, J29 ensure with a multimeter that there is no residual charge on the DC BUS capacitors.

Figure 23. Startup waveforms of the DAB

Full-load test

This test is used to verify the design functionalities up to full load. By following the procedure outlined below, the converter executes the startup phase, bringing both stages to nominal voltage conditions. Subsequently, the load can be increased until the target conditions of the converter are reached.

Table 13. Hardware and software requirements
Hardware	Software
STDES-BCBIDIRP	STM32 CUBE IDE
STDES-GAP2SICD x7	FW: STSW-BCBIDIR
STDES-PFCBIDIRC x2
Multi-channel DC Power supply
8 channel oscilloscope
ST-linkV2 isol + JTAG

Table 14. Hardware configurations
Hardware	Status
AC input voltage	Connected
DC load	Connected
DC auxiliary power supply (12 V, 7 V)	Connected

Table 15. Software configurations
Software	Status
DPC_PWM_INIT	PWM_Armed

Procedure to perform test

Connect the jumpers to enable MCU control of the relays (J39-J40-J41-J42 position 1-2, J35-J36-J37-J38 not connected). (Fig.6, first configuration)
Connect the transformer according to the instruction in chapter 3
Connect the low voltage auxiliary power supply (12 V, 7 V) respectively in U28 and U26 moving the selectors (J2, J3, J9, J10) towards V_ext to configure the external auxiliary power supply mode
Connect the AC power supply (J15 → PHA, J17 → PHB, J18 → PHC, J27 → N) without activation “output disabled”
Connect the five differential voltage probes: OUTA_DAB1- OUTB_DAB1 (TP94-TP95), OUTA_DAB2-OUTB_DAB2 (TP96-TP97) VBUS (TP92-TP84), VLOAD (TP126-TP127) PHA-N (J15-J27). Connect two hall-effect current probe on ILOAD, IA and a Rogowski probe on IDAB1
Connect the fan cables to U11 respecting the correct polarity. Connect a 12 V power supply to the U10 and provide the power. Move selector J8 in position 2-3 (PFC_FAN)
Connect the DC-Load taking care of the correct polarity at the connector. Positive cable to J28, negative cable to J29, the load must be set to Constant Current mode (CC) and must be disabled
Open the firmware: STSW_BCBIDIR_PFC inside the STSW-BCBIDIR, and verify that in the file project DPC_Application_Conf.h:

///DPC Finite State Machine DEFINE of STDES-BCBIDIR

#define DPC_PC_State_Init FSM_Idle

#define DPC_PWM_INIT PWM_Armed

#define DPC_TTC_MODE_INIT AC2DC_PFC_OPERATION

#define DPC_CTRL_INIT VOLTAGE_LOOP

///AC MAIN DEFINE of STDES-BCBIDIR

#define DPC_TTC_VAC_EU

///AC MAIN Connection DEFINE of STDES-BCBIDIR

#define DPC_AC_3W

///DC OUTPUT DEFINE of STDES-BCBIDIR

#define DPC_PFC_VDC_OUT 800

#define DPC_PFC_VDC_rampstart 760

///PROTECTION

//AC-DC

#define DPC_PFC_VAC_RMS_OVP 250

#define DPC_PFC_VAC_RMS_UVLOP 10

#define DPC_PFC_VAC_RMS_UVP 7

#define DPC_PFC_IAC_OCP 27

#define DPC_PFC_VDC_OVP 850

#define DPC_PFC_IDC_OCP 17
Connect the STLINK to the control board of the PFC (STDES-PFCBIDIRC on connector J1) stage as is shown in Figure 16 and flash the code
Open the firmware: STSW_BCBIDIR_DAB inside the STSW-BCBIDIR, and verify that in the file project DPC_Application_Conf.h:

/// DPC Finite State Machine DEFINE of STDES-DABBIDIR

#define DPC_DAB_ADPPWM

#define DPC_PC_State_Init FSM_Idle

#define DPC_FSM_RUN_INIT Run_Idle

#define DPC_FSM_STATE_INIT DPC_FSM_WAIT

#define DPC_CTRL_INIT DAB_VOLTAGE_LOOP

#define DPC_DAB_PWM_INIT PWM_Armed

#define DPC_DAB_MODE_INIT HV2LV

///DC OUTPUT DEFINE of STDES-DCDC_DAB

#define DPC_DAB_VDC_OUT 800

#define DPC_DAB_IDC_OUT 6

///PROTECTION HV2LV

#define DPC_DAB_VDCHV_OVP 850

#define DPC_DAB_VDCHV_UV 650

#define DPC_DAB_VDCHV_UVLO 30

#define DPC_DAB_VDCHV_MIN 750

#define DPC_DAB_IDCHV_OCP 17

#define DPC_DAB_IDCLV_OCP 17

#define DPC_DAB_VDCLV_OVP 850
Connect the STLINK to the control board of the DAB (STDES-PFCBIDIRC on connector P1) stage as is shown in Figure 16 and flash the code
Enable three-phase power supply (230 Vrms)

After powering the board (230 Vrms), setting a proper time base, and appropriately adjusting the zoom, waveforms like those in Full power test–double conversion will be displayed on the oscilloscope
Once the output voltage reaches the reference value (approximately 800 VDC), it will be possible to enable the load starting from 0 current up to full load
Shutdown:
- Gradually reduce the load to zero
- Disconnect the AC power supply
- Re-enable the load to discharge the capacitors of the output BUS
- Discharge the DC BUS with a suitable discharge circuit
DANGER: After performing the test and disconnecting the AC power supply, it is necessary to re-enable the load to discharge the output BUS capacitors. Furthermore, before touching connectors J20, J25, and J28, J29 ensure with a multimeter that there is no residual charge on the DC BUS capacitors
Figure 24. Full power test–double conversion

Measurements/waveforms/test data

Waveform

Waveforms analysis at:

V_IN = 230 Vrms
V_OUT = 800 V
f_{SW (PFC)} = 70 kHz
f_{SW (DC-DC)} = 100 kHz
PF = 0.996
Voltage regulation operating mode

Channel labels:

C1 = I_PRIM

C2 = V_DAB1

C3 = V_DAB2

C4 = I_A

C5 = V_A

C6 = I_DC

C7 = V_OUT

C8 = V_BUS

As can be seen from the first plot in Figure 25 Steady-state operations, the phase voltage and the relative current are perfectly aligned due to the high power factor (0.996). It is also possible to observe, from plots 6 and 7 respectively, the voltages at the ends of the HFT and the primary current of the Dual Active Bridge.

Waveforms analysis at:

V_IN = 230 Vrms
V_OUT = 800 V
f_{SW (PFC)} = 70 kHz
f_{SW (DC-DC)} = 100 kHz

Channel labels:

C1 = I_PRIM

C2 = V_DAB1

C3 = V_DAB2

C4 = I_A

C5 = V_A

C6 = I_DC

C7 = V_OUT

C8 = V_BUS

Figure 26 Soft start-up, shows the soft startup procedure implemented in the STDES-BCBIDIR. As can be seen from the fourth plot, the DC-BUS voltage (C8) is raised to the reference value following a controlled trend. After a configurable delay, the output voltage V_OUT (C7) is raised to the reference value also in a controlled manner.

Efficiency characterizations at:

V_IN = 230 Vrms
V_OUT = 800 V
f_{SW (PFC)} = 70 kHz
f_{SW (DC-DC)} = 100 kHz

Figure 27. Overall Efficiency

Schematic diagrams

Figure 28. STDES-BCBIDIR circuit schematic - Power board (1 of 18)

Figure 29. STDES-BCBIDIR circuit schematic - Power board (2 of 18)

Figure 30. STDES-BCBIDIR circuit schematic - Power board (3 of 18)

Figure 31. STDES-BCBIDIR circuit schematic - Power board (4 of 18)

Figure 32. STDES-BCBIDIR circuit schematic - Power board (5 of 18)

Figure 33. STDES-BCBIDIR circuit schematic - Power board (6 of 18)