Bottom cooling - host PCB design

To provide enough ‘thermal vias’, as the host PCB is a secondary heat sink for the device, it is important to use the recommended stack-up and to optimize the PCB layout beneath the package.

A significant power proportion is drawn from the package to ambient air through the host board by the paths detailed in the next sections (sorted by decreasing order of importance). The design rule implementation for ground and power connections is necessary for cooling and power distribution.

It is not possible to produce a set of rigid rules for layer construction within a PCB because each design has its own requirements.

The ground (GND) plane must have a low resistance (thermal and electrical) for all PCB areas. This improves signal quality and power dissipation. It also reduces EMI. The use of a ground layer and flooding of other layers with multiple vias maintain the resistance at a low level.

Placing as many thermal vias as possible on the ground and power planes just below the package, ensures that there is enough continuous copper between the adjacent vias for power distribution and thermal dissipation. A compromise must be found.

The thermal vias conduct heat from the device to the internal GND and power planes. These planes spread the heat inside the PCB that acts as a planar heat sink.

On the outer layers, some GND areas can be added wherever functional tracks are absent. Connect these areas to GND by a network of vias wherever possible.

These GND areas help in heat spreading and dissipation along the board. The figure below shows the principle of additional GND areas and vias to the GND plane.

This section shows examples of thermal analysis performed on a discovery kit (STM32H747XI MCU), an evaluation board (STM32MP157), and an internal validation board (STM32MP135 MPU).

This thermal analysis has been done on a Discovery kit with an STM32H747XI device (STM32H747I-DISCO), without casing (see the figure below).

The temperature sensor connected to the ADC3 VINP [18] input channel, is used for T_J measurement.

The T_J measurements are read via the USART2 using the DMA transfer, without CPU interruption.

As stated in STM32 thermal parameters, the dissipated power varies with T_J. The power consumption in this example is measured for different T_J values (see the table and the figure below).

The figures and table below detail the thermal measurements performed at T_A = 25 °C.

Once the design HDC is defined (by measurement at 25 °C), and assuming that this HDC is constant at 25 °C and 85 °C, the operating point of the design at 85 °C is given by translating the HDC at 85 °C. See the figure and table below.

In conclusion, the STM32H7 device is safe, with no thermal runaway, and T_J remaining < 125 °C.