Over the past decades, transistors have been continuously scaled down in size to increase performance and reduce power consumption, leading to better electronics devices, able to do more useful, important, and valuable things faster, more clearly, and more efficiently; what the marketers call “an enhanced user experience.”
Reaching the limits of Moore’s law
In recent years, as the transistor has shrunk to a size now below a few tens of nanometers, the effort has increased the challenges for every new generation of technology. One example is leakage current, which because transistors are so small, now represents a significant proportion of its power consumption.
In order to continue to deliver higher performance--while keeping the leakage under control--bulk-silicon transistors have become ever more complex, adding additional manufacturing steps and more recently considering a move to a new, expensive, 3D architecture.
The FD-SOI innovations
ST, together with its partners, alternatively introduced new innovations in silicon process technology that incrementally leverage existing manufacturing approaches. Fully Depleted Silicon On Insulator, or FD-SOI, is a planar process technology that delivers the benefits of reduced silicon geometries while actually simplifying the manufacturing process.
|Learn more about FD-SOI technology|
|FD-SOI: The only technology to not break Moore’s law|
|FD-SOI: Efficiency at all levels|
|White paper on our 28nm FD-SOI standard-cell libraries offer|