| Author | beginning argument ( Replies received: 4 ) |
| mvi |
 Posted 15-04-2008 at 21:38 |
Registered on :
04-08-2008
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Hi,
Is it possible to change the HSICAL bits on the fly while the HSI and PLL generated SYSCLK is running?
Because the PLL needs some time to lock on the frequency Im having doubts about it. Any confirmations?
"The trimming step is 40 kHz between two consecutive HSICAL steps." How accurate is this statement quoted from the reference manual?
Thanks.
-Mad
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| lanchon |
Posted 16-04-2008 at 06:32 |
Registered on :
11-02-2008
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> How accurate?
if it's not speced, you probably won't get an answer to that.
I'd expect that tolerance to be similar to the HSI tolerance *before factory calibration*, which I guess is not speced either, but if I had to guess I'd say around +/-30%.
I believe that to expect the step to be in the 20 to 80KHz range would be reasonable.
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| ben.edwards |
 Posted 02-09-2008 at 20:56 |
Registered on :
09-02-2008
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I am interested to know if you tried changing the HSICAL bits on the fly. STOne-32, do you know if this will work?
We have a system with a high quality 1-second tick generated by another device, and we'd like to use this to calibrate the HSI. We don't want to shut off the PLL every second to adjust the HSI frequency, so if changing HSICAL causes the PLL to lose lock, we won't use this method.
Note: We want to adjust HSICAL up or down by only 1 step at a time.
Thanks in advance,
Ben
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| STOne-32 |
 Posted 03-09-2008 at 21:40 |
Registered on :
05-29-2007
From STMicroelectronics
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Hi,
Note also that the HSI is already calibrated to 1% at 25°C and the maximum deviation is 3%.
The HSI Frequency is based on an internal RC circuitry . Once calibrated at start-up the deviation of the "R" resistance at run-time will depend only when the temperature or VDD is changing. So basically in most of applications, VDD is constant except when powered from a battery, thus make us to say that only the temperature will affect the HSI Frequency. However the temperature variation in most of application is not varying suddenly each 1s. Taking into account all of these parameters, we can from time to time re-calibrate again ( using an Input capture of one timer if you have a reference frequency or for example using the LSE output pin if yoy are using a 32.768Khz RTC quartz) The HSI if the temperature or VDD is changing.
Back to your question, to perform a calibration while PLL is Running and locked is not safe and may cause a PLL unlock if the input Jitter created by the HSICAL variation is not acceptable even only by one step.
Regards,
STOne-32.
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| Kuni |
Posted 04-09-2008 at 09:37 |
Registered on :
10-30-2003
From Taiwan
Messages : 139
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How about LSI? % of accuracy? deviation versus temperature?
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HSI Calibration