| Author | beginning argument ( Replies received: 4 ) |
| abhishek.ramanujan |
 Posted 02-09-2008 at 12:02 |
Registered on :
08-07-2008
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Hello everybody
I am trying to restart a timer from the ISR routine. here is the description. I have timer2 configured with PWM of 50% duty cycle (TIM2_CH1). I also have the ADC triggering a watchdog interrupt if the converted value is greater that 0xC00(upper threshold). When the watchdog interrupt is fired, I need the TIM2_CH1 to immediately switch to 0 (irrespective of the duty cycle) and the timer should be restarted from the ISR. The period of the TIM2_CH1 is 1ms (1 kHz PWM). Duty cycle is fixed to be 50% is the ADC value remains less than 0xC00.
Any help is appreciated. Thanks in advance
AR
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| adamajames |
Posted 02-09-2008 at 12:21 |
Registered on :
08-26-2008
Messages : 9
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My guess (and it is a guess)
You'll need to generate an immediate UEV (update event) (after you've reset your Timer 2) to reload the registers.
From the STM32 Manual:
In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
Adam
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| lanchon |
Posted 02-09-2008 at 12:49 |
Registered on :
11-02-2008
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do you want a) the output at a constant low value while analog value > 0xC00, or b) to resync the phase of the PWM after each "< 0xC00 to > 0xC00" transition?
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| abhishek.ramanujan |
Posted 02-09-2008 at 13:03 |
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08-07-2008
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Thanks for your interest lanchon. The need is TIM2_CH1 running a PWM of 1KHz, 50% duty cycle for all ADC value < C00 and if ADC > C00, timer pulse reset to 0 at the time of WDG interrupt and the timer should restart if the ADC value is less than C00 (at a later time).
__|^^|__|^^|__|^^|__|^^|__ for ADC values < C00
t0 t1 t2 t3
if at time t1 if ADC value > C00, output should be as
__|^^|__|^|___ the timer may restart at time t2 if ADC < C00 and continue
t0 t1 t2
50% duty cycle, else remain 0.
NOTE: t1 as at the second pulse, t2 at the start of third pulse and t3 at the start of 4th pulse.
Thanks again
AR
[ This message was edited by: abhishek.ramanujan on 02-09-2008 13:06 ]
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| lanchon |
Posted 03-09-2008 at 09:38 |
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11-02-2008
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I don't remember much about the analog watchdog, but I think it has two events, over and undervoltage, with separate high and low marks. you might want to use 0xC00+x and 0xC00-x as the marks to provide 2x hysteresis.
use high and low mark ISRs to stop and start the timer. do you think something is wrong with this simple design?
(in the high mark ISR you may want to disable the high mark int and enable the low mark int, and vice-versa in the low mark ISR. this would implement the hysteresis. maybe the hardware already does something like this so these actions are not needed, I don't know.)
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Timer2 restart in ISR