The CMOS090 design platform is based on ST's 90nm (0.09 micron) CMOS process technology. Designed as a modular process, it allows maximum flexibility in combining multiple features, such as:
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Dual threshold library elements |
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Various IP modules -- like microprocessor, DSP, hi-speed links |
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Process options for e-Drams, analog or RF options |
The 90nm design platform is intended for System-on-Chip (SoC) and ASIC solutions that target wireless, low-power, consumer, networking and hi-speed applications.
Based on dual-damascene copper technology, it allows 6 to 9 metal layers of interconnect and a library density of more than 400,000 gates per mm2.
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Core Process Features |
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65nm poly length |
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Dual Vt MOS transistors |
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Dual gate oxide |
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Dedicated process flavors for high performance or low power |
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Dual-damascene copper for interconnect |
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Low-k (k = 2.9) dielectric |
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6 to 9 metal layers for interconnect |
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0.28um metalization pitch |
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Analog/RF capabilities |
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Fully compatible with e-DRAM |
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Various power supplies supported: 3.3V, 2.5V, 1.8V, 1.2V, 1V |
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Library Features |
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Dual standard cell libraries optimized for speed and density |
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Total of >1000 core cells |
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Core lib supply voltage of 1.0V or 1.2V |
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Gate delay of 11 ps (standard Vt) |
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Gate density of 430Kgates/mm2 |
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Full suite of high-density memory compilers (> 10) for single port SRAM, dual port, ROM and register files, covering high speed or low power applications |
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E-DRAM modules for improved memory integration |
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I/O interface at 1.2V, 1.8V, 2.5V and 3.3V both for pad limited or core limited designs |
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Specific IO interfaces including SSTL2, HSTL, LVTTL, USB 1.1 and 2.0, PCIX, UDMA, LVDS |
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Hi-speed links at 2.4Gb |
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A broad portfolio of analog and RF IPs covers the need for single system super integration |
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Design Tools Platform |
The CMOS090 ASIC platform provides a complete concurrent design environment for all phases from RTL to PGtape.
Based on physical synthesis with the best tools from major EDA suppliers, it manages full-hierarchical design with hardware and software macros, and includes full Power Planning and ClockTree synthesis capabilities. DFT, including Scan, BIST and IDDQ techniques are all included in the design flow.
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