AN4894 · Application noteHow to use EEPROM emulation on STM32 MCUs
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EEPROM emulation memory footprint

EEPROM emulation memory footprint

Table 9 Memory footprint for EEPROM emulation mechanism details the footprint of the EEPROM emulation driver in terms of flash memory, RAM, and stack size for some of the products covered by this application note.

The figures shown have been determined using the IAR EWARM 8.42.2 (or later) tool with a high size optimization level. Note that this algorithm does not use heap.

Table 9. Memory footprint for EEPROM emulation mechanism
STM32 series or lineRequired1 code and data size in bytes
FlashSRAM
STM32L4 series425612
STM32L4+ series428612
STM32L5 series472812
STM32G0 series381212
STM32G4 series494612
STM32WB series539216
STM32WB series2332814
STM32WL3x line33968
STM32U0 series492012
STM32U3 series467212
STM32U5 series554812
STM32C0 series50988
STM32H5 series530012
STM32H5 series using high-cycle data area248812

Table 9 Memory footprint for EEPROM emulation mechanism does not include the flash memory size used for EEPROM emulation itself. Refer to the formula given in Computing the required size of flash memory for EEPROM emulation to calculate the corresponding flash memory size.

Note also that the application program (main.c) implements the VarDataTab[] variable to store the EEPROM element values. Its size is 4000 bytes for 1000 32-bit elements.

For flexibility, this variable is placed in RAM in the provided example. Moreover, VarDataTab[] can easily be removed as most user applications do not need to have a RAM copy of the elements stored in flash memory.

1 Based on 1000 elements (16-bit address, 16-bit CRC, and 32-bit data).
2 Example with Bluetooth® LE communication.

EEPROM emulation timing

This section describes the timing parameters associated with the EEPROM emulation driver based on 1000 32-bit variables, except for the STM32U5 and STM32H5 series, which have 1000 96-bit variables. Moreover, the STM32H5 series including high-cycle data area have 1000 32-bit variables.

All timing measurements are performed with the following conditions:

  • At VDD = 3.3 V
  • With execution from flash memory (from the bank not used for EEPROM variables, when dual bank is used)
  • At room temperature
  • Based on 100 operations for each type of operation.
Table 10 EEPROM emulation timings for different targets lists the timing values for the EEPROM emulation driver in these conditions for some of the products covered by this application note. In other conditions, for instance for a different number of variables, cycles endurance or a different MCU frequency, these timings can differ significantly.
Table 10. EEPROM emulation timings for different targets

TargetConditionsOperationMin.MeanMax.
STM32L476G-DISCO
  • System clock = 80 MHz
  • ART enabled
  • flash memory prefetch disabled
  • Endurance = 100 kcycles
EEPROM initialization with forced erase1904.4 ms1.2215 s2.0212 s
EEPROM initialization with conditional erase126.1 ms365.56 ms1.2499 s
Write operation in EEPROM90 μs- 3344.90 ms
Read operation from EEPROM49.3 μs47.412 μs311.5 μs
EEPROM cleanup1900.13 ms900.27 ms900.38 ms
EEPROM cleanup IT1900 ms900.19 ms900.38 ms
NUCLEO-L4R5ZI
  • System clock = 80 MHz5
  • ART enabled
  • flash memory prefetch disabled
  • Endurance = 100 kcycles
EEPROM initialization with forced erase1509.6 ms741.69 ms884 ms
EEPROM initialization with conditional erase125.8 ms466.91 ms776.9 ms
Write operation in EEPROM90 μs- 3307.20 ms
Read operation from EEPROM49 μs75.639 μs314.3 μs
EEPROM cleanup1461.8 ms461.90 ms462 ms
EEPROM cleanup IT1461.8 ms461.86 ms462 ms
NUCLEO-L552ZE-Q
  • System clock = 110 MHz
  • ICACHE disabled
  • Endurance = 10 kcycles
EEPROM initialization with forced erase1111.1 ms365.10 ms670 ms
EEPROM initialization with conditional erase121.5 ms267.5 ms680 ms
Write operation in EEPROM90 μs- 3580.18 ms
Read operation from EEPROM410 μs149.3 μs485.6 μs
EEPROM cleanup1109.80 ms109.85 ms109.89 ms
EEPROM cleanup IT1109.81 ms109.85 ms109.88 ms
NUCLEO-G071RB
  • System clock = 64 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase1111.4 ms251.17 ms814.4 ms
EEPROM initialization with conditional erase121.47 ms233.43 ms792.9 ms
Write operation in EEPROM90 μs- 3702.18 ms
Read operation from EEPROM414 μs102.16 μs592 μs
EEPROM cleanup1110.37 ms110.39 ms110.40 ms
EEPROM cleanup IT1110.40 ms110.41 ms110.43 ms
NUCLEO-G431RB
  • System clock = 170 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase1110.3 ms179.33 ms349.4 ms
EEPROM initialization with conditional erase12600 μs160.90 ms356.3 ms
Write operation in EEPROM90 μs- 3260.67 ms
Read operation from EEPROM46 μs74.242 μs170 μs
EEPROM cleanup1109.86 ms109.89 ms109.89 ms
EEPROM cleanup IT1109.89 ms109.90 ms109.92 ms
P-NUCLEO-WB55.Nucleo6
  • System clock = 64 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase167.27 ms276.83 ms561.32 ms
EEPROM initialization with conditional erase121.86 ms258.65 ms539.78 ms
Write operation in EEPROM90 μs- 3476.26 ms
Read operation from EEPROM411 μs289.25 μs570 μs
EEPROM cleanup165.82 ms65.867 ms65.92 ms
EEPROM cleanup IT164.90 ms64.966 ms65.92 ms
NUCLEO-WL33CC17
  • System clock = 64 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase1108.1 ms436 ms1.007 s
Write operation in EEPROM141.2 us- 360.17 ms
Read operation from EEPROM423.2 us92.36 us733.5 us
EEPROM cleanup142.137 ms42.139 ms42.142 ms
EEPROM cleanup IT142.137 ms42.140 ms42.142 ms
NUCLEO-U031R8
  • System clock = 48 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase1112.4 ms426.97 ms922.4 ms
EEPROM initialization with conditional erase122.26 ms385.4 ms920.5 ms
Write operation in EEPROM115.4 μs- 3709.1 ms
Read operation from EEPROM426.89 μs92.18 μs157.5 μs
EEPROM cleanup1109.8 ms109.87 ms110 ms
EEPROM cleanup IT1109.9 ms109.92 ms110 ms
NUCLEO-U385RG-Q
  • System clock = 96 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase136.02 ms129.92 ms347 ms
EEPROM initialization with conditional erase120.500 ms129.44 ms368 ms
Write operation in EEPROM77.74 μs- 3277.5 ms
Read operation from EEPROM45.1 μs40.56 μs94.4 μs
EEPROM cleanup135.92 ms35.97 ms35.98 ms
EEPROM cleanup IT135.92 ms35.97 ms36.02 ms
NUCLEO-U575ZI-Q
  • System clock = 160 MHz
  • ICACHE disabled
  • Endurance = 10 kcycles
EEPROM initialization with forced erase14 ms207 ms410 ms
EEPROM initialization with conditional erase121.6 ms164.8 ms328 ms
Write operation in EEPROM129 μs- 3540 ms
Read operation from EEPROM48 μs234 μs460 μs
EEPROM cleanup14.623 ms4.74 ms4.852 ms
EEPROM cleanup IT14.623 ms4.73 ms4.844 ms
NUCLEO-C031C6
  • System clock = 48 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase188.8 ms557 ms926.9 ms
EEPROM initialization with conditional erase1223.3 ms519 ms938.9 ms
Write operation in EEPROM116.7 μs- 3838.5 ms
Read operation from EEPROM428.4 μs92.65 μs156.9 μs
EEPROM cleanup187.8 ms87.83 ms87.89 ms
EEPROM cleanup IT187.81 ms87.83 ms87.86 ms
NUCLEO-H563ZI
  • System clock = 240 MHz
  • Endurance = 10 kcycles
EEPROM initialization with forced erase15.126 ms61.25 ms173.1 ms
EEPROM initialization with conditional erase120.415 ms56.48 ms167.7 ms
Write operation in EEPROM33.72 μs- 3174.1 ms
Read operation from EEPROM43.18 μs29.7 μs143.1 μs
EEPROM cleanup14.931 ms4.94 ms4.939 ms
EEPROM cleanup IT14.931 ms4.93 ms4.938 ms
NUCLEO-H563ZI using high-cycle data area
  • System clock = 240 MHz
  • Endurance = 100 kcycles
EEPROM initialization with forced erase1175.3 ms333.9 ms519.5 ms
EEPROM initialization with conditional erase12160.5 ms304.4 ms457.1 ms
Write operation in EEPROM126.2 μs- 3370.2 ms
Read operation from EEPROM43.802 μs114.63 μs226.1 μs
EEPROM cleanup14.922 ms4.93 ms4.939 ms
EEPROM cleanup IT14.922 ms4.93 ms4.943 ms
Note:

These timing measurements are provided to give the reader an idea of the emulation firmware performance for different STM32 series. They are based on 100 operations for each type of operation. Thus, they are not an absolute reference. It is possible to find different minimums, maximums and even means (especially if the measurement conditions are modified).

1 The maximum initialization time and cleanup time depend on the number of flash memory EEPROM pages used, and the time to erase one page. (See the section "Flash memory characteristics" in the STM32 product datasheet). The time taken to erase flash memory EEPROM pages = number of pages * tERASE.
2 When the application ensures the EEPROM emulation cannot be interrupted by an asynchronous reset or power failure, a conditional erase can be used. It is more efficient in terms of execution time and also in terms of EEPROM endurance (refer to Page header recovery for more details).
3 The typical write time is close to the minimal write time as there is no data transfer in most cases. The maximum value refers to a write operation that generates a data transfer.
4 The minimum value refers to a read operation of the last element stored in the flash memory and the maximum value refers to a read operation of the first element stored in the flash memory.
5 Timing measurements for the STM32L4+ series board (NUCLEO-L4R5ZI) has been done for an 80 MHz system clock so that a comparison can be done with the STM32L4 series (NUCLEO-L476RG). However, the NUCLEO-L4R5ZI can be pushed up to 120 MHz while the NUCLEO-L476RG is limited at 80 MHz. The measurements for the other boards are done for the maximum system clock.
6 Data taken from the example without Bluetooth® LE capabilities.
7 For NUCLEO-WL33C1, EEPROM initialization timing with conditional erase is not specified, because the device does not support differentiation between a wake-up from Deepstop mode and an asynchronous reset or power failure.
8 The maximum initialization time and cleanup time depend on the number of flash memory EEPROM pages used, and the time to erase one page. (See the section "Flash memory characteristics" in the STM32 product datasheet). The time taken to erase flash memory EEPROM pages = number of pages * tERASE.
9 When the application ensures the EEPROM emulation cannot be interrupted by an asynchronous reset or power failure, a conditional erase can be used. It is more efficient in terms of execution time and also in terms of EEPROM endurance (refer to Page header recovery for more details).
10 The typical write time is close to the minimal write time as there is no data transfer in most cases. The maximum value refers to a write operation that generates a data transfer.
11 The minimum value refers to a read operation of the last element stored in the flash memory and the maximum value refers to a read operation of the first element stored in the flash memory.
12 Timing measurements for the STM32L4+ series board (NUCLEO-L4R5ZI) has been done for an 80 MHz system clock so that a comparison can be done with the STM32L4 series (NUCLEO-L476RG). However, the NUCLEO-L4R5ZI can be pushed up to 120 MHz while the NUCLEO-L476RG is limited at 80 MHz. The measurements for the other boards are done for the maximum system clock.
13 Data taken from the example without Bluetooth® LE capabilities.
14 For NUCLEO-WL33C1, EEPROM initialization timing with conditional erase is not specified, because the device does not support differentiation between a wake-up from Deepstop mode and an asynchronous reset or power failure.