Power supply management

The STM32U5 devices require a 1.71 to 3.6 V operating voltage supply (V_DD).

The independent supplies listed below, can be provided for specific peripherals:

• V_DD = 1.71 V to 3.6 V

  V_DD is the external power supply for the I/Os, the internal regulator, and the system analog such as reset, power management, and internal clocks. V_DD is provided externally through the VDD pins.

• V_DDA = 1.62 V (ADCs/COMPs/DACs/OPAMPs) / 1.8 V (VREFBUF) to 3.6 V

  V_DDA is the external-analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers, and comparators. The V_DDA voltage level is independent from the V_DD voltage. The VDDA pin must preferably be connected to the V_DD voltage supply when these peripherals are not used.

  Note:

  In case the VDDA pin is left at high impedance or is tied to VSS, the maximum input voltage that can be applied on the I/Os with "_a" I/O structure, is reduced (refer to device datasheet for more details).

• V_DDSMPS = 1.71 V to 3.6 V

  V_DDSMPS is the external power supply for the SMPS step-down converter. It is provided externally through the VDDSMPS pin, and must be connected to the same supply as VDD pin when the SMPS is used in the application. When the SMPS is not used, it is recommended to connect both V_DDSMPS and V_LXSMPS to ground.

• V_LXSMPS
  The VLXSMPS pin is the switched SMPS step-down converter output.

  Note:

  The SMPS output can not be used to power external components.

• V_DD11

  V_DD11 is a digital core supply provided through the internal SMPS step-down converter VLXSMPS pin. VDD11 pins (two or three) are present only on packages with internal SMPS, connected to a total of 4.7 µF (typical) external capacitors.

• V_CAP
  V_CAP is the digital core supply, from the internal LDO regulator. VCAP pins (one or two) are present only on packages with LDO only (without SMPS), connected to a total of 4.7 µF (typical) external capacitor.

  Note:

  • In case there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF capacitor, for a total around 4.4 µF.
  • The SMPS power supply pins (VLXSMPS, VDD11, VDDSMPS, VSSSMPS) are available only on packages with SMPS. In such packages, the STM32U5 devices embed two regulators, one LDO and one SMPS in parallel, to provide the V_CORE supply to digital peripherals. A 4.7 μF total external capacitor and a 2.2 µH coil are required on VDD11 pins.
  • The flash memory is supplied by V_CORE and V_DD.

• V_DDUSB = 3.0 V to 3.6 V
  V_DDUSB is the external-independent power supply for USB transceivers. The V_DDUSB voltage level is independent from the V_DD voltage. The VDDUSB pin must preferably be connected to the V_DD voltage supply when the USB is not used.

  Note:

  In case the VDDUSB pin is left at high impedance or is tied to VSS, the maximum input voltage that can be applied on the I/Os with "_u" I/O structure, is reduced (refer to device datasheet for more details).

• V_DD11USB = 1.0 V to 1.26 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)

  V_DD11USB is the external power supply for the USB transceiver. This supply is only available on specific packages and must be connected to VDD11.

• V_DDIO2 = 1.08 V to 3.6 V
  V_DDIO2 is the external power supply for 14 I/Os (port G[15:2]). The V_DDIO2 voltage level is independent from the V_DD voltage, and must preferably be connected to V_DD when PG[15:2] is not used.

  Note:

  On small packages, V_DDA, V_DDIO2, or V_DDUSB independent power supplies may not be present as a dedicated pin, and are internally bonded to a VDD pin. They are neither present when the related features are not supported on the product.

• V_BAT = 1.55 V to 3.6 V

  V_BAT is the power supply when V_DD is not present (through power switch) for RTC, TAMP, external clock 32 kHz oscillator, backup registers, and optionally backup SRAM.

• V_REF-, V_REF+

  V_REF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer (VREFBUF) when enabled. The VREF+ pin can be grounded when ADC and DAC are not active.

  The internal voltage reference buffer supports four output voltages that are configured with the VRS[2:0] field in VREFBUF_CSR register:

  • V_REF+ around 1.5 V. This requires V_DDA ≥ 1.8 V.
  • V_REF+ around 1.8 V. This requires V_DDA ≥ 2.1 V.
  • V_REF+ around 2.048 V. This requires V_DDA ≥ 2.4 V.
  • V_REF+ around 2.5 V. This requires V_DDA ≥ 2.8 V.

  VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA pins, respectively.

  When the VREF+ pin is double-bonded to VDDA in a package, the internal VREFBUF is not available, and must be kept disabled.

  V_REF- must always be equal to V_SSA.

• V_DDDSI = 1.71 V to 3.6 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)

  V_DDDSI is the external power supply for the DSI controller. It is provided externally through the VDDDSI supply pin, and must be connected to the same supply as VDD pin.

• V_DD11DSI = 1.0 V to 1.26 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)

  V_DD11DSI is the external power supply for the DSI transceiver and must be connected to VDD11.

The following figures present an overview of the STM32U5 devices power supply, depending on the SMPS presence.

In devices without SMPS, the V_DD supply source feeds the I/Os and system analog peripherals (such as PLLs and reset block). The V_CORE power supply for digital peripherals and memories is generated from the LDO.

To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply that can be separately filtered and shielded from noise on the PCB.

The voltage supply input of the analog peripherals is available on a separate VDDA pin. An isolated supply ground connection is provided on VSSA pin.

The V_DDA supply voltage can be different from V_DD. After reset, the analog peripherals supplied by V_DDA are logically and electrically isolated and therefore are not available. The isolation must be removed before using these peripherals, by setting the ASV bit in PWR_SVMCR, once the V_DDA supply is present.

The V_DDA supply can be monitored by analog voltage monitors (AVM), and compared with two thresholds (1.6 V for AVM1 or 1.8 V for AVM2). For more details, refer to the device datasheet and section Peripheral voltage monitoring (PVM) of document AN5373_general-info.html#id_14462__entry_msl_1fh_dvb.

When a single supply is used, the VDDA pin can be externally connected to the same V_DD supply, through an external filtering circuit, to ensure a noise-free V_DD reference voltage.

Some I/Os from port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can range from 1.08 V to 3.6 V, and is provided externally through the VDDIO2 pin. The V_DDIO2 voltage level is completely independent from V_DD or V_DDA.

The VDDIO2 pin is available only for some packages (refer to the pinout details in the datasheet for the I/O list).

After reset, the I/Os supplied by V_DDIO2 are logically and electrically isolated and are therefore not available. The isolation must be removed before using any I/O from PG[15:2], by setting the IO2SV bit in PWR_SVMR, once the V_DDIO2 supply is present.

The V_DDIO2 supply is monitored by the V_DDIO2 voltage monitoring (IO2VM) and compared with the internal reference voltage (3/4 V_REFINT, around 0.9 V).

For more details, refer to the device datasheet and section Peripheral voltage monitoring (PVM) of document AN5373_general-info.html#id_14462__entry_msl_1fh_dvb.

The USB transceivers are supplied from a separate V_DDUSB power supply. V_DDUSB range is from 3.0 V to 3.6 V and is completely independent from V_DD or V_DDA.

After reset, the USB features supplied by V_DDUSB are logically and electrically isolated, and are therefore not available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the PWR_SVMR register, once the V_DDUSB supply is present.

The V_DDUSB supply is monitored by the USB voltage monitoring (UVM) and compared with the internal reference voltage (V_REFINT, around 1.2 V). For more details, refer to the device datasheet and section Peripheral voltage monitoring (PVM) of document AN5373_general-info.html#id_14462__entry_msl_1fh_dvb.

For STM32U59x/5Ax/5Fx/5Gx devices only, the USB high-speed transceiver can be supplied from an optional power supply V_DD11USB. V_DD11USB range is from 1.0 V to 1.26 V and must be connected to V_DD11.

To retain the content of the backup registers and supply the RTC when V_DD is turned off, the VBAT pin can be connected to an optional backup voltage, supplied by a battery or by another source.

The VBAT pin powers RTC, TAMP, LSE oscillator, and PC13 to PC15 I/Os. That allows the RTC to operate even when the main power supply is turned off.

The backup SRAM is optionally powered through the VBAT pin, when the BREN bit is set in PWR_BDCR1.

The switch to the V_BAT supply is controlled by the power-down reset embedded in the reset block.

If no external battery is used in the application, it is recommended to connect the VBAT pin externally to V_DD with a 100 nF external ceramic decoupling capacitor.

They can be selected when the application runs, depending on the application requirements. The SMPS allows the power consumption to be reduced. However, the noise generated by the SMPS may impact some peripheral behaviors, requiring the application to switch to LDO when running the peripheral, in order to reach the best performances.

Except for Standby circuitries and the Backup domain, LDO or SMPS can be used in all voltage scaling ranges (range 1/2/3/4), in all Stop modes (Stop 0/1/2/3), and in Standby mode with SRAM2. Refer to the low-power mode summary table in document AN5373_general-info.html#id_14462__entry_msl_1fh_dvb.

On some packages, the SMPS supply pins are not available, consequently only the LDO might be used to supply V_CORE domain.

Some I/Os embed analog switches for both analog peripherals (ADCs, COMPs, DACs) and TSC (touch sensing controller) functions. These switches are by default supplied by V_DDA. However, they can be supplied by a V_DDA voltage booster or by V_DD, depending on the configuration of ANASWVDD and BOOSTEN bits in SYSCFG_CFGR1.

It is recommended to supply the I/O switches with the highest voltage value between V_DDA, V_DDA booster, and V_DD.

The analog switches for TSC function are supplied by V_DD.