Serial-wire debug (SWD) pin assignment

After reset, the pins used for the SWD are assigned as dedicated pins that can be immediately used by the debugger host.

However, the MCU offers the possibility to disable the SWD, therefore releasing the associated pins for GPIO use.

For more details on how to disable SWD port, refer to section I/O pin alternate function multiplexer and mapping of document AN6011_general_info.html#id_59975__entry_msl_1fh_dvb.

Having embedded pull-up and pull-down resistors removes the need to add external resistors.

For technical reasons, it is best to use a multilayer PCB, with a separate layer dedicated to ground (V_SS) and another dedicated to the V_DD supply.

This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for ground and power supply.

In order to improve analog performance, the user must use separate supply sources for V_DD and V_DDA, and place the decoupling capacitors as close as possible to the device.

The power supplies (V_SS, V_DD, V_SSA, V_DDA, V_DDUSB, V_DDIO2, V_DDDSI, or V_DDSMPS) must be implemented close to the ground line to minimize the area of the supplies loop. This is because the supply loop acts as an antenna, and acts as the main transmitter and receiver of EMI. All component‑free PCB areas must be filled with additional grounding to create a kind of shielding (especially when using single‑layer PCBs).

All power-supply and ground pins must be properly connected to the power supplies. These connections (including pads, tracks, and vias) must have the lowest possible impedance. This is typically achieved with thick track widths and, preferably, the use of dedicated power-supply planes in multilayer PCBs.

In addition, each power supply pair must be decoupled with filtering ceramic capacitors (100 nF) and a tantalum or ceramic capacitor of about 10 μF, connected in parallel on the device.

Some packages use a common VSS pin for several VDD pins, instead of a pair of power pins (one VSS for each VDD). In that case, the capacitors must be between each VDD pin and the common VSS pin. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB. Typical values are 10 to 100 nF, but exact values depend on the application needs.

The figure below shows the typical layout of such a VDD/VSS pin pair.

All microcontrollers are designed for a variety of applications and often a particular application does not use 100 % of the MCU resources.

The reference designs shown in the next sections are based on STM32U5 devices in LQFP144 and TFBGA216 packages. This reference design can be tailored to any STM32U5 device with a different package, using the pin correspondence given in Design reference for a STM32U5 device (with and without SMPS) and Design reference for a STM32U599/5A9/5F9/5G9 device (with SMPS).