The following sections describe the errata of the applicable devices and provide a workaround where available. They are grouped by device functions.
The applicable devices are based on Arm® Cortex® core.
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.
The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved.
Reference manual and errata notice for the Arm® Cortex®-M33 core revision r0p4 is available from http://infocenter.arm.com. Only applicable information from the Arm errata notice is replicated in this document.
A load or store which causes an unaligned access to device memory results in an UNALIGNED UsageFault exception. However, if the region is not accessible because of the MPU access permissions (as specified in MPU_RBAR.AP), then the resulting MemManage fault is prioritized over the UsageFault.
The MemManage fault caused by the access permission violation is prioritized over the UNALIGNED UsageFault exception because of the memory attributes.
None. However, it is expected that no existing software is relying on this behavior since it was permitted in Armv7‑M.
On LQFP and UFQFPN packages, the LSE crystal oscillator clock frequency can be incorrect when PC13 is toggling in input or output (for example when used for RTC_OUT1).
The external clock input (LSE bypass) is not impacted by this limitation.
The WLCSP and UFBGA packages are not impacted by this limitation.
Avoid toggling PC13 when LSE is used on LQFP and UFQFPN packages.
None.
The PWR_S3WU flag (WUFx in PWR_WUSR) is automatically cleared when clearing the internal wake-up source flag.
Set the PWR_S3WU interrupt with a lower priority than the internal source interrupt (RTC or TAMP). Consequently, upon wake-up from Stop 3 mode, the RTC or TAMP interrupt is serviced first. Then, the PWR_S3WU interrupt is entered without the corresponding flag (WUFx in PWR_WUSR) being set. This interrupt service routine can be returned without clearing any flag.
None.
If an operation is started while the write buffer is waiting for the next data (STRT or OPTSTRT is set while WDW is already set), the PGSERR flag is set and the programming sequence is expected to be aborted. However, the WDW bit remains set and the flash programming operation remains stuck, waiting for the second word to be written.
Write the second word to the write buffer to either start the programming (if the programming sequence is correct) or raise a new error, which resets the WDW flag.
None.
When using the JTAG debug port in Debug mode, the connection with the debugger is lost if the NJTRST pin (PB4) is used as a GPIO or for an alternate function other than NJTRST. Only the 4-wire JTAG port configuration is impacted.
Use the SWD debug port instead of the full 4-wire JTAG port.
The MSI clock frequency can be up to 25% lower than expected upon exit from Standby or Stop 3 mode, for a maximum of 200 µs.
In case accuracy is needed, wait for 200 µs after exiting Standby or Stop 3 mode before using the MSI.
None.
MSIK can be used as kernel clock by the MDF1 and ADF1 by configuring the MDF1SEL and ADF1SEL bitfields of RCC_CCIPRx registers.
Once selected as kernel clock source for MDF1 or ADF1 peripherals, MSIK can no longer be disabled using the MSIKON bits of the RCC_CR register. This is because MDF1 and ADF1 request their kernel clock by default after reset.
If the application requests an entry in Stop 0, Stop 1, or Stop 2 mode, the selected MSIK kernel clock remains enabled leading to an overconsumption in this mode. The Stop 3 mode is not concerned by this limitation. MDF1 is not concerned for Stop 2 mode.
Before disabling the MSIK clocks, configure MDF1SEL and ADF1SEL to HCLK.
In case the application wants to enter Stop 0 or Stop 1 mode, and the MDF1 and ADF1 are not used during Stop mode, then configure MDF1SEL and ADF1SEL bitfields to HCLK before entering Stop mode. Upon Stop mode exit, restore the required MSIK kernel clock with the MDF1SEL and ADF1SEL bitfields. In case the application wants to enter Stop 2 mode and the ADF1 is not used during Stop mode, the same procedure is needed only for ADF1SEL.
In case the application wants to enter Stop 0, Stop 1, or Stop 2 mode and the MDF1 or ADF1 peripheral is used during Stop mode (Stop 0 and Stop 1 modes only for MDF1), then simply configure the MDF1SEL and ADF1SEL bitfields to required MSIK kernel clock. These peripherals request their kernel clock when they need it.
The backup domain reset may be missed upon backup domain power‑on subsequent to a VBAT power‑off, in VBAT mode, if the VBAT voltage during the power‑off phase drops to a few mV window before starting to rise again. In this critical window, the flip‑flops are no longer able to safely retain the information, and the backup domain reset has not yet been triggered. This window is located in the range between 100 mV and 700 mV, with the exact position depending mainly on the device and on the temperature. The issue only occurs when MONEN = 0 in the PWR_BDCR1 register (backup domain supply and temperature monitoring are disabled).
This missed reset results in unpredictable values of the backup domain registers, which may cause a spurious behavior such as driving the LSCO output pin on PA2, raising an unexpected tamper event preventing the SRAM2 or PKA access, or influencing any of the backup domain functions.
Apply one of the following measures to avoid the incorrect backup domain reset:
The workaround consists in calculating the CRC of the backup domain registers: RCC_BDCR and RTC/TAMP registers, excluding bits modified by hardware.
The CRC result can be stored in the backup register instead of a fixed value. This value needs to be updated for each modification of values covered by CRC, such as by using CRC peripheral.
At the very beginning of the boot code, insert the following software sequence:
Both security and privilege configuration of the extended interrupts and event controller (EXTI) must be locked when the LOCK bit of the EXTI lock register (EXTI_LOCKR) is set. The EXTI security configuration register (EXTI_SECCFGR1) is locked as expected, but the EXTI privilege configuration register (EXTI_PRIVCFGR1) can still be modified when the LOCK bit is set.
None.
A system reset occurs when the MCU is in Stop 2 mode on LDO regulator, with at least, one RAM in power‑down (SRAMx, Caches, or peripheral SRAMs). This may lock the device in a high consumption state (dozens of mA). The IWDG, the external NRST pin, and the BOR thresholds 1 to 4 are the reset sources that create this limitation.
Only a power-on sequence recovers from this state: VDD must drop below VBOR0 (brownout reset minimum threshold value), then raise to its expected value.
Keep all SRAMs powered on during Stop 2 mode that is all xRAMxPD/PDS bits in PWR_CRx registers must be kept at their reset state.
This is a documentation error rather than a device limitation.
When the application needs to get the ECC error flags and addresses status without servicing the associated interrupts, the RAMCFG SEIE/DEIE interrupts must be enabled with the associated NVIC RAMCFG vector 5 disabled.
The PVD_IN IO analog switches are not functional when supplied by VDDA (BOOSTEN = ANASWVDD = 0 in SYSCFG_CFGR1 register) or when supplied by booster voltage (BOOSTEN = 1 in SYSCFG_CFGR1 register). Consequently, PVD_IN does not work properly.
There is no PVD limitation when PVD_IN is not used.
When MSI operates in PLL mode, the device continuously monitors the MSI input clock signal. Upon detecting a failure, it generates an interrupt and unlocks the MSI PLL. In this state, the MSI output clock accuracy degrades.
Some devices may falsely detect a failure even when the MSI input clock signal is correct and valid.
The probability of a spurious PLL unlock is higher at low temperatures and low VCORE voltages.
In the interrupt handler, disable MSI PLL mode and enable it again. Returning to the PLL locked state takes approximately 600 µs to 1 ms.