ADC1
ADC_AWDy_OUT reset by non-guarded channels
Description
ADC_AWDy_OUT is set when a guarded conversion of a regular or injected channel is outside the programmed thresholds. It is reset after the end of the next guarded conversion that is inside the programmed thresholds.
However, the ADC_AWDy_OUT signal is also reset at the end of conversion of non-guarded channels, both regular and injected.
Workaround
When ADC_AWDy_OUT is enabled, it is recommended to use only the ADC channels that are guarded by a watchdog.
If ADC_AWDy_OUT is used with ADC channels that are not guarded by a watchdog, take only ADC_AWDy_OUT rising edge into account.
Injected data stored in the wrong ADC_JDRx registers
Description
When the AHB clock frequency is higher than the ADC clock frequency after the prescaler is applied (ratio > 10), if a JADSTP command is issued to stop the injected conversion (JADSTP bit set to 1 in ADC_CR register) at the end of an injected conversion, exactly when the data are available, then the injected data are stored in ADC_JDR1 register instead of ADC_JDR2/3/4 registers.
Workaround
Before setting JADSTP bit, check that the JEOS flag is set in ADC_ISR register (end of injected channel sequence).
14-bit ADC offset error and integral linearity error values are increased in datasheets
Description
STM32U535 and STM32U545 datasheets revision 1 (DS14216 and DS14217) specify that:
- The offset error maximum value is ±5 LSB in singled ended mode, while the correct value is ±12 LSB.
- The integral linearity error maximum value is ±5 LSB in singled ended mode, while the correct value is ±7 LSB.
This is a documentation error rather than a device limitation. This error has no impact on the ADC accuracy.
Workaround
None.
ADC I/Os analog switches are not functional when supplied by VDDA
Description
The ADC IO analog switches are not functional when supplied by VDDA (BOOSTEN = ANASWVDD = 0 in SYSCFG_CFGR1 register), or when supplied by booster voltage (BOOSTEN = 1 in SYSCFG_CFGR1 register).
Consequently, the ADC IO switch impedance is higher than expected, and the maximum external input impedance (RAIN) for ADC1 and ADC4 tables are wrong in the datasheets.
The analog switches booster is not functional, consequently the datasheet "Analog switches booster characteristics" table is not applicable to silicon rev. Z.Workaround
For all VDD and VDDA voltage settings:
- Disable the booster (BOOSTEN = 0 in SYSCFG_CFGR1 register).
- Supply the analog switch by VDD (ANASWVDD = 1 in SYSCFG_CFGR1 register).
- When VDD < 2.4V, increase the ADC sampling time compared to values provided in datasheets.
Table 5 Maximum ADC1 R AIN shows the maximum external input impedance values for ADC1.
| Resolution | RAIN (Ω) | New sampling time [ns] | New sampling cycle at 5 MHz | New sampling cycle at 55 MHz |
|---|---|---|---|---|
|
14bits 2 LSB gabarit | 47 | 337 | 5 | 20 |
| 68 | 342 | 5 | 20 | |
| 100 | 399 | 5 | 36 | |
| 12 bits | 47 | 320 | 5 | 20 |
| 68 | 318 | 5 | 20 | |
| 100 | 327 | 5 | 20 | |
| 150 | 334 | 5 | 20 | |
| 220 | 340 | 5 | 20 | |
| 330 | 342 | 5 | 20 | |
| 470 | 389 | 5 | 36 | |
| 10 bits | 47 | 304 | 5 | 20 |
| 68 | 307 | 5 | 20 | |
| 100 | 309 | 5 | 20 | |
| 150 | 310 | 5 | 20 | |
| 220 | 319 | 5 | 20 | |
| 330 | 325 | 5 | 20 | |
| 470 | 348 | 5 | 20 | |
| 680 | 370 | 5 | 36 | |
| 1 000 | 403 | 5 | 36 | |
| 1 500 | 461 | 5 | 36 | |
| 2 200 | 599 | 5 | 36 | |
| 8 bits | 47 | 292 | 5 | 20 |
| 68 | 293 | 5 | 20 | |
| 100 | 294 | 5 | 20 | |
| 150 | 298 | 5 | 20 | |
| 220 | 298 | 5 | 20 | |
| 330 | 308 | 5 | 20 | |
| 470 | 306 | 5 | 20 | |
| 680 | 334 | 5 | 20 | |
| 1 000 | 364 | 5 | 36 | |
| 1 500 | 395 | 5 | 36 | |
| 2 200 | 461 | 5 | 36 | |
| 3 300 | 543 | 5 | 36 | |
| 4 700 | 664 | 5 | 68 | |
| 6 800 | 882 | 5 | 68 | |
| 10 000 | 1 362 | 12 | 391 |
Table 6 Maximum ADC4 R AIN shows the maximum external input impedance values for ADC4.
| Resolution | RAIN (Ω) | New sampling time [ns] | New sampling cycle at 35 MHz | New sampling cycle at 55 MHz |
|---|---|---|---|---|
| 12 bits | 47 | 658 | 40 | 40 |
| 68 | 685 | 40 | 40 | |
| 100 | 725 | 40 | 80 | |
| 150 | 793 | 40 | 80 | |
| 220 | 885 | 40 | 80 | |
| 330 | 1 031 | 40 | 80 | |
| 470 | 1 220 | 80 | 80 | |
| 680 | 1 498 | 80 | 815 | |
| 1 000 | 1 925 | 80 | 815 | |
| 1 500 | 2 585 | 815 | 815 | |
| 2 200 | 4 460 | 815 | 815 | |
| 3 300 | 5 448 | 815 | 815 | |
| 4 700 | 7 593 | 815 | 815 | |
| 6 800 | 10 791 | 815 | 815 | |
| 10 000 | 15 506 | 815 | NA | |
| 15 000 | 22 556 | 815 | NA | |
| 22 000 | 31 761 | NA | NA | |
| 33 000 | 44 836 | NA | NA | |
| 10 bits | 47 | 203 | 8 | 13 |
| 68 | 211 | 8 | 13 | |
| 100 | 220 | 13 | 13 | |
| 150 | 248 | 13 | 20 | |
| 220 | 261 | 13 | 20 | |
| 330 | 301 | 13 | 20 | |
| 470 | 350 | 13 | 20 | |
| 680 | 456 | 20 | 40 | |
| 1 000 | 585 | 40 | 40 | |
| 1 500 | 787 | 40 | 80 | |
| 2 200 | 1 069 | 40 | 80 | |
| 3 300 | 1 510 | 80 | 815 | |
| 4 700 | 2 067 | 80 | 815 | |
| 6 800 | 2 892 | 815 | 815 | |
| 10 000 | 4 126 | 815 | 815 | |
| 15 000 | 5 992 | 815 | 815 | |
| 22 000 | 8 760 | 815 | 815 | |
| 33 000 | 12 922 | 815 | 815 | |
| 47 000 | 17 801 | 815 | NA | |
| 8 bits | 47 | 105 | 8 | 8 |
| 68 | 106 | 8 | 8 | |
| 100 | 109 | 8 | 8 | |
| 150 | 118 | 8 | 8 | |
| 220 | 128 | 8 | 8 | |
| 330 | 145 | 8 | 13 | |
| 470 | 165 | 8 | 13 | |
| 680 | 200 | 8 | 13 | |
| 1 000 | 249 | 13 | 20 | |
| 1 500 | 330 | 13 | 20 | |
| 2 200 | 442 | 20 | 40 | |
| 3 300 | 620 | 40 | 40 | |
| 4 700 | 844 | 40 | 80 | |
| 6 800 | 1 180 | 80 | 80 | |
| 10 000 | 1 681 | 80 | 815 | |
| 15 000 | 2 456 | 815 | 815 | |
| 22 000 | 3 510 | 815 | 815 | |
| 33 000 | 5 109 | 815 | 815 | |
| 47 000 | 7 018 | 815 | 815 | |
| 6 bits | 47 | 74 | 4 | 8 |
| 68 | 73 | 4 | 8 | |
| 100 | 74 | 4 | 8 | |
| 150 | 77 | 4 | 8 | |
| 220 | 78 | 4 | 8 | |
| 330 | 82 | 4 | 8 | |
| 470 | 95 | 4 | 8 | |
| 680 | 113 | 8 | 8 | |
| 1 000 | 141 | 8 | 13 | |
| 1 500 | 181 | 8 | 13 | |
| 2 200 | 243 | 13 | 20 | |
| 3 300 | 335 | 13 | 20 | |
| 4 700 | 456 | 20 | 40 | |
| 6 800 | 636 | 40 | 40 | |
| 10 000 | 912 | 40 | 80 | |
| 22 000 | 1 922 | 80 | 815 | |
| 33 000 | 2 830 | 815 | 815 | |
| 47 000 | 3 954 | 815 | 815 |