ES0587 · Errata sheetSTM32U535xx and STM32U545xx device errata
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ADC4

ADC4 conversion error when used simultaneously with ADC1

Description

The ADC4 conversion is disturbed when carried out simultaneously with an ADC1 conversion and results in an ADC4 conversion error. The error is due to a VREF+ disturbance during an ADC1 sampling phase, and occurs regardless of which VREF+ is provided: either by external reference, or by VREFBUF.

Workaround

ADC1 and ADC4 analog converter clocks must be identical (same clock source, same frequency, and same phase) to avoid any disturbance. This is possible only when both ADC prescalers are programmed without any division factor. The bitfields of the both registers listed below must be set to 0b0000:

  • ADC1 prescaler: PRESC[3:0] in the ADC12_CCR register
  • ADC4 prescaler: PRESC[3:0] in the ADC4_CCR register

ADC1 and ADC4 analog converter clock frequencies must not exceed 55 MHz and the ADC4 clock duty cycle must be set to between 45% and 55%. Selecting AHB clock as the ADC kernel clock limits the whole AHB to 55 MHz. Other independent clock sources can be used to avoid this drawback. As a result, the triggers from timers, that are clocked by AHB clock, have an uncertainty due to trigger synchronization delay from timers AHB clock to ADC asynchronous kernel clock. In case PLL output pll2_r_ck is used as ADC kernel clock, the PLL division (controlled by the PLL2R[6:0] bitfield in the RCC_ RCC_PLL2_DIVR register) must be set to an even division (division by 2, 4, and so on) to guarantee a 50% ratio.

Note:

The use of ADC kernel clock division factor is possible if ADC1 and ADC4 do not convert simultaneously.

VREFBUF_OUT voltage overshoots in Range 4, Stop 1 or Stop 2 mode

Description

The VREFBUF_OUT output voltage overshoots when started:
  • While the regulator is in Range 4,
  • While the device is in Stop 1 or Stop 2 mode.

Workaround

Modify the regulator voltage Range to Range 1, 2, or 3 before enabling the voltage reference buffer.

COMP I/Os analog switches are not functional when supplied by VDDA

Description

The COMP IO analog switches are not functional when supplied by VDDA (BOOSTEN = ANASWVDD = 0 in SYSCFG_CFGR1 register) or when supplied by booster voltage (BOOSTEN = 1 in SYSCFG_CFGR1 register). Consequently, COMP does not work properly.

Workaround

For all VDD and VDDA voltage settings:
  1. Disable the booster (BOOSTEN = 0 in SYSCFG_CFGR1 register).
  2. Supply the analog switch by VDD (ANASWVDD = 1 in SYSCFG_CFGR1 register).

OPAMP I/Os analog switches are not functional when supplied by VDDA

Description

The OPAMP IO analog switches are not functional when supplied by VDDA (BOOSTEN = ANASWVDD = 0 in SYSCFG_CFGR1 register) or when supplied by booster voltage (BOOSTEN = 1 in SYSCFG_CFGR1 register). Consequently, OPAMP does not work properly.

Workaround

For all VDD and VDDA voltage settings:
  1. Disable the booster (BOOSTEN = 0 in SYSCFG_CFGR1 register).
  2. Supply the analog switch by VDD (ANASWVDD = 1 in SYSCFG_CFGR1 register).

TSC I/Os analog switches are not functional when supplied by VDDA

Description

The TSC IO analog switches are not functional when supplied by VDDA (BOOSTEN = ANASWVDD = 0 in SYSCFG_CFGR1 register), or when supplied by booster voltage (BOOSTEN = 1 in SYSCFG_CFGR1 register). Consequently, TSC does not work properly.

Note:

When ASV = 0 in PWR_SVMCR register, the IO analog switches are supplied by VDD, so the limitation is not present.

Workaround

When ASV = 1, for all VDD and VDDA voltage settings:
  1. Disable the booster (BOOSTEN = 0 in SYSCFG_CFGR1 register).
  2. Supply the analog switch by VDD (ANASWVDD = 1 in SYSCFG_CFGR1 register).

Data transfer from TAMP_BKPxR to key registers must be done only in ascending order when KEYSEL[2:0] is set to 010 or 100

Description

The KEYSEL[2:0] bitfield of the SAES_CR register defines the source of the key information to use in the SAES cryptographic core:
  • When KEYSEL[2:0] is set to 010, the boot hardware key (BHK), stored in tamper-resistant secure backup registers, is entirely transferred into the key registers upon a secure application performing a single read of all TAMP_BKPxR registers (x = 0 to 3 for KEYSIZE = 0, x = 0 to 7 for KEYSIZE = 1).
  • When KEYSEL[2:0] is set to 100, the XOR combination of DHUK and BHK is entirely transferred into the key registers upon a secure application performing a single read of all TAMP_BKPxR registers (x = 0 to 3 for KEYSIZE = 0, x = 0 to 7 for KEYSIZE = 1).

Some revisions of the reference manual may wrongly specify that the read operation can be performed either in ascending or descending order, while it must be performed always in ascending order.

This is a documentation issue rather than a product limitation.

Workaround

No application workaround is required, provided that the read operation to the TAMP_BKPxR registers is always done in ascending order.

Device may remain stuck in LPTIM interrupt when entering Stop mode

Description

This limitation occurs when disabling the low-power timer (LPTIM).

When the user application clears the ENABLE bit in the LPTIM_CR register within a small time window around one LPTIM interrupt occurrence, then the LPTIM interrupt signal used to wake up the device from Stop mode may be frozen in active state. Consequently, when trying to enter Stop mode, this limitation prevents the device from entering low-power mode and the firmware remains stuck in the LPTIM interrupt routine.

This limitation applies to all Stop modes and to all instances of the LPTIM. Note that the occurrence of this issue is very low.

Workaround

In order to disable a low power timer (LPTIMx) peripheral, do not clear its ENABLE bit in its respective LPTIM_CR register. Instead, reset the whole LPTIMx peripheral via the RCC controller by setting and resetting its respective LPTIMxRST bit in the relevant RCC register.

ARRM and CMPM flags are not set when APB clock is slower than kernel clock

Description

When LPTIM is configured in one shot mode and APB clock is lower than kernel clock, there is a chance that ARRM and CMPM flags are not set at the end of the counting cycle defined by the repetition value REP[7:0]. This issue can only occur when the repetition counter is configured with an odd repetition value.

Workaround

To avoid this issue, the following formula must be respected:

{ARR, CMP} ≥ KER_CLK / (2* APB_CLK),

where APB_CLK is the LPTIM APB clock frequency, and KER_CLK is the LPTIM kernel clock frequency. ARR and CMP are expressed in decimal value.

Example: The following example illustrates a configuration where the issue can occur:
  • APB clock source (MSI) = 1 MHz, kernel clock source (HSI) = 16 MHz
  • The repetition counter is set with REP[7:0] = 0x3 (odd value)
The above example is subject to issues, unless the user respects:

{CMP, ARR} ≥ 16 MHz / (2 * 1 MHz)

→ ARR must be ≥ 8 and CMP must be ≥ 8
Note:

REP set to 0x3 means that effective repetition is REP+1 (= 4) but the user must consider the parity of the value loaded in the LPTIM_RCR register (=3, odd) to assess the risk of issue.

Interrupt status flag is cleared by hardware upon writing its corresponding bit in LPTIM_DIER register

Description

When any interrupt bit of the LPTIM_DIER register is modified, the corresponding flag of the LPTIM_ISR register is cleared by hardware.

Workaround

None.