| 16-Feb-2023 | 1 | Initial release |
| 28-Jun-2023 | 2 | Added errata:- System: Incorrect backup domain reset with VBAT and VDD supplied by different power sources
- EXTI LOCK bit does not lock privilege configuration
- Device may be locked upon system reset under Stop 2 mode
- SRAM ECC error flags and addresses are updated only if interrupt is enabled
- The ADC I/Os analog switch voltage booster is not functional
- OCTOSPI: At least six cycles memory latency must be set when DQS is used for HyperBus™ memories
- Data write discarded in memory-mapped mode if a write to a misaligned address is directly followed by a request to the same address
- ADC1: 14-bit ADC offset error and integral linearity error values are increased in datasheets
- USART: Wrong data received by SPI slave receiver in Autonomous mode with CPOL = 1
- Received data may be corrupted upon clearing the ABREN bit
- Noise error flag set while ONEBIT is set
Renamed LPUART limitation: Wrong data received when the communication nodes are two LPUART instances into Possible LPUART transmitter issue when using low BRR[15:0] value Removed errata not applicable for this product: - ADC1: Unexpected regular conversion when two consecutive injected conversions are performed in Dual interleaved mode
- Channel selection not reset in Bulb mode when regular conversions are stopped by DMA or ADSTP
- ADC slave data may be shifted in Dual regular simultaneous mode
- TSC: Inhibited acquisition in short transfer phase configuration
- TIM: Consecutive compare event missed in specific conditions
- Output compare clear not working with external counter reset
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| 21-Dec-2023 | 3 | Added errata:- System: Flash programming can remain stuck in case of programming sequence error
- VDDUSB is internally connected to VDD in WLCSP56 packages
- OCTOSPI: Setting the ABORT bit does not generate an error on the AHB bus for undefined-length incremental burst transfers
- SAES: Data transfer from TAMP_BKPxR to key registers must be done only in ascending order when KEYSEL[2:0] is set to 010 or 100
- USB: Buffer description table update completes after CTR interrupt triggers
Modified errata: - System: LSE crystal oscillator may be disturbed by transitions on PC13
- OCTOSPI: Read data corruption after a few bytes are skipped when crossing a four-byte boundary
- USART: Data corruption due to noisy receive line
Removed errata not applicable for this product: - OCTOSPI: Received data corrupted after arbitration ownership toggles when using clock mode 3 and no DQS for read direction
- Deadlock can occur under specific conditions
- USB: False wakeup detection for last K‑state not terminated by EOP or reset before suspend
- ESOF interrupt timing desynchronized after resume signaling
- Incorrect CRC16 in the memory buffer
- Possible packet memory overrun/underrun at low APB frequency
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| 04-Apr-2024 | 4 |
Added Rev. Y.
Added errata: - Read data corruption when a wrap transaction is followed by a linear read to the same MSB address
- Transactions are limited to 8 Mbytes in OctaRAM™ memories
- Command response and receive data end bits not checked
- TSC I/Os analog switches are not functional when supplied by VDDA
- COMP I/Os analog switches are not functional when supplied by VDDA
- OPAMP I/Os analog switches are not functional when supplied by VDDA
- PVD_IN I/Os analog switches are not functional when supplied by VDDA
Modified errata: ADC I/Os analog switches are not functional when supplied by VDDA
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| 17-Jun-2025 | 5 | Added errata:- TIFRE flag wrongly set in slave PCM long frame mode if FIXCH = 1
- TIFRE flag never set in slave PCM/I2S mode if FIXCH = 0
- Incorrect name of AES suspend registers
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| 01-Jul-2026 | 6 |
Added:
Removed: Incorrect name of AES suspend registers
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