Desynchronization under specific condition with edge filtering enabled
Description
FDCAN may desynchronize and incorrectly receive the first bit of the frame if:
- the edge filtering is enabled (the EFBI bit of the FDCAN_CCCR register is set), and
- the end of the integration phase coincides with a falling edge detected on the FDCAN_Rx input pin
If this occurs, the CRC detects that the first bit of the received frame is incorrect, flags the received frame as faulty and responds with an error frame.
Note:
This issue does not affect the reception of standard frames.
Workaround
Disable edge filtering or wait for frame retransmission.
Tx FIFO messages inverted under specific buffer usage and priority setting
Description
Two consecutive messages from the Tx FIFO may be inverted in the transmit sequence if:
- FDCAN uses both a dedicated Tx buffer and a Tx FIFO (the TFQM bit of the FDCAN_TXBC register is cleared), and
- the messages contained in the Tx buffer have a higher internal CAN priority than the messages in the Tx FIFO.
Workaround
Apply one of the following measures:
- Ensure that only one Tx FIFO element is pending for transmission at any time:
The Tx FIFO elements may be filled at any time with messages to be transmitted, but their transmission requests are handled separately. Each time a Tx FIFO transmission has completed and the Tx FIFO gets empty (TFE bit of FDACN_IR set to 1) the next Tx FIFO element is requested.
- Use only a Tx FIFO:
Send both messages from a Tx FIFO, including the message with the higher priority. This message has to wait until the preceding messages in the Tx FIFO have been sent.
- Use two dedicated Tx buffers (for example, use Tx buffer 4 and 5 instead of the Tx FIFO). The following pseudo-code replaces the function in charge of filling the Tx FIFO:
Write message to Tx Buffer 4 Transmit Loop: Request Tx Buffer 4 - write AR4 bit in FDCAN_TXBAR Write message to Tx Buffer 5 Wait until transmission of Tx Buffer 4 complete (IR bit in FDCAN_IR), read TO4 bit in FDCAN_TXBTO Request Tx Buffer 5 - write AR5 bit of FDCAN_TXBAR Write message to Tx Buffer 4 Wait until transmission of Tx Buffer 5 complete (IR bit in FDCAN_IR), read TO5 bit in FDCAN_TXBTO
USB
Buffer description table update completes after CTR interrupt triggers
Description
During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.