Memory-mapped write error response when DQS output is disabled
Description
If the DQSE control bit of the OCTOSPI_WCCR register is cleared for memories without DQS pin, it results in an error response for every memory-mapped write request.
Workaround
When doing memory-mapped writes, set the DQSE bit of the OCTOSPI_WCCR register, even for memories that have no DQS pin.
Byte possibly dropped during an SDR read in clock mode 3 when a transfer gets automatically split
Description
When reading a continuous stream of data from sequential addresses in a serial memory, the OCTOSPI can interrupt the transfer and automatically restart it at the next address when features generating transfer splits (CSBOUND, REFRESH, TIMEOUT or MAXTRAN) are active. Thus, a single continuous transfer can effectively be split into multiple smaller transfers.
When the OCTOSPI is configured to use clock mode 3 (CKMODE bit of the OCTOSPI_DCR1 register set) and a continuous stream of data is read in SDR mode (DDTR bit of the OCTOSPI_CCR register cleared), the last byte sent by the memory before an automatic split gets dropped, thus causing all the subsequent bytes to be seen one address earlier.
Workaround
Use clock mode 0 (CKMODE bit of the OCTOSPI_DCR1 register cleared) when in SDR mode.
Deadlock or write-data corruption after spurious write to a misaligned address in OCTOSPI_AR register
Description
Upon writing a misaligned address to OCTOSPI_AR just before switching to memory-mapped mode (without first triggering the indirect write operation), with the OCTOSPI configured as follows:
- FMODE = 00 in OCTOSPI_CR (indirect write mode)
- DQSE = 1 in OCTOSPI_CCR (DQS active)
then, the OCTOSPI may be deadlocked on the first memory-mapped request or the first memory-mapped write to memory (and any sequential writes after it) may be corrupted.
An address is misaligned if the address is:
- Odd and the OCTOSPI is configured to send two bytes of data to the memory every cycle (octal-DTR mode or dual-quad-DTR mode), or
- Not a multiple of four when the OCTOSPI is configured to send four bytes of data to the memory (16-bit DTR mode or dual-octal DTR mode).
If the OCTOSPI_AR register is reprogrammed with an aligned address (without triggering the indirect write between the two writes to OCTOSPI register), the data sent to the memory during the indirect write operation are also corrupted.
Workaround
None.
Read data corruption after a few bytes are skipped when crossing a four-byte boundary
Description
A memory-mapped read is corrupted when the following sequence occurs:
- An 8- or 16-bit read is performed in a four-byte window, and the last byte of this window is not read.
- Any read in the next four-byte window is done before the completion of the previous read memory prefetch.
OCTOSPI immediately responds to this read request, even before the data are read from memory, thus resulting in incorrect data read.
If the next read operations are issued to consecutive addresses, then the read data are also corrupted.
This limitation is not present when the SDMMC accesses the OCTOSPI since the SDMMC performs only 32-bit read accesses.
Workaround
Apply one of the following measures:
-
Perform only 32-bit memory-mapped read accesses. For CPU read accesses, enable ICACHE and/or DCACHE and configure the OCTOSPI memory as cacheable (CACHE only performs 32-bit read accesses).
For system DMA, use only 32-bit data size for read accesses.
- If this is not possible and an 8-bit or 16-bit read is done at the beginning of a four-byte window, ensure that the next access is not a read from the next four-byte window or that the second access occurs after the data at the skipped addresses are prefetched from memory.
At least six cycles memory latency must be set when DQS is used for HyperBus memories
Description
For HyperBus™ memories, the TACC[7:0] bitfield of the OCTOSPI_HLCR register enables the setting of the memory latency in number of clock cycles. These dummy cycles are inserted between the address and the data phases during read operations.
When the DQS signal is used for HyperBus™ memories, and the number of latency clock cycles programmed in TACC[7:0] is lower than six, a deadlock occurs during read operations.
Workaround
Configure the memory and the octo-SPI controller to have at least six clock cycles of latency.
Data write discarded in memory-mapped mode if a write to a misaligned address is directly followed by a request to the same address
Description
In memory-mapped mode with DQS enabled, a data write is discarded if the write targets a misaligned address and is directly followed by a request (cycle by cycle on AHB) to the same address.
An address is misaligned if the address is odd and the OCTOSPI is configured to send two bytes of data to the memory on every cycle that is targeted by one of the following modes:
- Octal DTR
- Dual-quad DTR
Workaround
Use one of the following measures:
- Configure the OCTOSPI to issue commands to aligned addresses, that is to an even address when two bytes are transferred during each clock cycle.
- Avoid consecutive back-to-back (AHB cycle by cycle) accesses to the memory after a write to a memory mapped at the same address. Instead, insert a NOP (no operation) or a software delay between the two accesses.
Setting the ABORT bit does not generate an error on the AHB bus for undefined-length incremental burst transfers
Description
An AHB error is expected to be generated when the ABORT bit of the OCTOSPI_CR register is set while a request is ongoing.
Instead, the controller does not trigger any AHB error if the ongoing request is an undefined-length incremental burst AHB transfer.
An AHB error is generated for all other transfer types.
Workaround
When possible, wait for the end of the transfer before setting the ABORT bit.
Read data corruption when a wrap transaction is followed by a linear read to the same MSB address
Description
If a wrap transaction is followed by a linear read having the same MSB start address as the wrap (), then the linear read is wrongly considered as a sequential transaction to the previous one, taking back the prefetched data and causing data corruption.
Notice that for a wrap transaction, the prefetch starts after the last address of the wrap window.
Workaround
As prefetch cannot be disabled, there is no workaround. However, the issue is seldom encountered since wrap operations are mostly initiated by the internal cache to refresh its cacheline. All the other masters must avoid retrieving data by using a linear read access to the same MSB address as the wrap, which has been just completed.
Transactions are limited to 8 Mbytes in OctaRAM memories
Description
When the controller is configured in Macronix OctaRAM™ mode, by setting the MTYP[2:0] bitfield of the OCTOSPI_DCR1 register to 011, only 13 bits of row address are decoded and sent to the memory, meaning that only 8 K of 1-Kbyte blocks can be accessed (8 Mbytes).
Note:
This limitation is not present for PSRAMs or HyperRAM™ memories.
Workaround
None.
Variable latency is not supported when a refresh collision occurs during a write access to some OctaRAM memories
Description
When the memory type (MTYP[2:0] bitfield of the OCTOSPI_CR register) is configured to 0b011 to target an OctaRAM™ memory, the host controller does not support the variable latency requested by the external memory if a refresh collision occurs during the write access. For example, some OctaRAM™ memories, such as ISSI memories, request extra latency cycles for write accesses during refresh collision. In this case, the controller does not sample the DQS input signal during the instruction phase, and cannot detect the extra latency requested by the external memory for the refresh operation.This results in data corruption.
Some OctaRAM™ memories do not request any additional latency for write access during refresh cycles. It is required only when the refresh occurs during a read access. In this case, no issue can be observed.
Workaround
When the application targets an OctaRAM™ memory that requests extra latency cycles for write access during refresh collision, force the fixed latency mode in the configuration register of the external memory. There is no constraint about read access, since both variable and fixed latency modes are supported.