Errata sheet

STM32U535xx and STM32U545xx device errata

Rev 6 - July 2026

Applicability

This document applies to the part numbers of STM32U535xx and STM32U545xx devices and the device variants as stated in this page.

It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0456.

Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation erratum. The term errata applies both to limitations and documentation errata.

Table 1. Device summary
ReferencePart numbers
STM32U535xxSTM32U535CB, STM32U535CC, STM32U535CE, STM32U535JE, STM32U535NC, STM32U535NE, STM32U535RB, STM32U535RC, STM32U535RE, STM32U535VC, STM32U535VE
STM32U545xxSTM32U545CE, STM32U545JE, STM32U545NE, STM32U545RE, STM32U545VE

Table 2. Device variants
ReferenceSilicon revision codes
Device marking1REV_ID2
STM32U535xx and STM32U545xxZ0x1001
Y0x1003
1 Refer to the device datasheet for how to identify this code on different types of packages.
2 REV_ID[15:0] bitfield of DBGMCU_IDCODE register.

Summary of device errata

The following table gives a quick reference to the STM32U535xx and STM32U545xx device limitations and their status:

ALimitation applicable. Workaround available
NLimitation applicable. No workaround available
PLimitation applicable. Partial workaround available
-Limitation not applicable.

Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on the device or in only a subset of operating modes, of the function concerned.

Table 3. Summary of device limitations
FunctionSectionLimitationStatus
Rev. ZRev. Y
Core Access permission faults are prioritized over unaligned device memory faults Access permission faults are prioritized over unaligned device memory faults N N
System LSE crystal oscillator may be disturbed by transitions on PC13 LSE crystal oscillator may be disturbed by transitions on PC13 N N
The PWR_S3WU interrupt is generated for internal wake-up sources (WUSELx = 11) The PWR_S3WU interrupt is generated for internal wake-up sources (WUSELx = 11) A A
Flash programming can remain stuck in case of programming sequence error Flash programming can remain stuck in case of programming sequence error A A
HardFault on wake-up from Stop mode may occur in debug mode HardFault on wake-up from Stop mode may occur in debug mode N N
Full JTAG configuration without NJTRST pin cannot be used Full JTAG configuration without NJTRST pin cannot be used A A
Too low MSI frequency upon exit from Standby or Stop 3 mode Too low MSI frequency upon exit from Standby or Stop 3 mode A A
PWR_BDCR1 is not write-protected by DBP PWR_BDCR1 is not write-protected by DBP N N
MSIK clock cannot be stopped when used as kernel clock by MDF1 or ADF1 MSIK clock cannot be stopped when used as kernel clock by MDF1 or ADF1 A A
Incorrect backup domain reset with VBAT and VDD supplied by different power sources Incorrect backup domain reset with VBAT and VDD supplied by different power sources A A
EXTI LOCK bit does not lock privilege configuration EXTI LOCK bit does not lock privilege configuration N N
Device may be locked upon system reset under Stop 2 mode Device may be locked upon system reset under Stop 2 mode P -
PVD_IN I/Os analog switches are not functional when supplied by VDDA PVD_IN I/Os analog switches are not functional when supplied by VDDA A A
Spurious MSI PLL unlock Spurious MSI PLL unlock P P
OCTOSPI Memory-mapped write error response when DQS output is disabled Memory-mapped write error response when DQS output is disabled P P
Byte possibly dropped during an SDR read in clock mode 3 when a transfer gets automatically split Byte possibly dropped during an SDR read in clock mode 3 when a transfer gets automatically split A A
Deadlock or write-data corruption after spurious write to a misaligned address in OCTOSPI_AR register Deadlock or write-data corruption after spurious write to a misaligned address in OCTOSPI_AR register N N
Read data corruption after a few bytes are skipped when crossing a four-byte boundary Read data corruption after a few bytes are skipped when crossing a four-byte boundary A A
At least six cycles memory latency must be set when DQS is used for HyperBus memories At least six cycles memory latency must be set when DQS is used for HyperBus memories A A
Data write discarded in memory-mapped mode if a write to a misaligned address is directly followed by a request to the same address Data write discarded in memory-mapped mode if a write to a misaligned address is directly followed by a request to the same address A A
Setting the ABORT bit does not generate an error on the AHB bus for undefined-length incremental burst transfers Setting the ABORT bit does not generate an error on the AHB bus for undefined-length incremental burst transfers P P
Read data corruption when a wrap transaction is followed by a linear read to the same MSB address Read data corruption when a wrap transaction is followed by a linear read to the same MSB address N N
Transactions are limited to 8 Mbytes in OctaRAM memories Transactions are limited to 8 Mbytes in OctaRAM memories N N
Variable latency is not supported when a refresh collision occurs during a write access to some OctaRAM memories Variable latency is not supported when a refresh collision occurs during a write access to some OctaRAM memories P P
ADC1 ADC_AWDy_OUT reset by non-guarded channels ADC_AWDy_OUT reset by non-guarded channels A A
Injected data stored in the wrong ADC_JDRx registers Injected data stored in the wrong ADC_JDRx registers A A
ADC I/Os analog switches are not functional when supplied by VDDA ADC I/Os analog switches are not functional when supplied by VDDA A -
ADC4 ADC4 conversion error when used simultaneously with ADC1 ADC4 conversion error when used simultaneously with ADC1 P P
VREFBUF VREFBUF_OUT voltage overshoots in Range 4, Stop 1 or Stop 2 mode VREFBUF_OUT voltage overshoots in Range 4, Stop 1 or Stop 2 mode A A
COMP COMP I/Os analog switches are not functional when supplied by VDDA COMP I/Os analog switches are not functional when supplied by VDDA A A
OPAMP OPAMP I/Os analog switches are not functional when supplied by VDDA OPAMP I/Os analog switches are not functional when supplied by VDDA A A
TSC TSC I/Os analog switches are not functional when supplied by VDDA TSC I/Os analog switches are not functional when supplied by VDDA A A
LPTIM Device may remain stuck in LPTIM interrupt when entering Stop mode Device may remain stuck in LPTIM interrupt when entering Stop mode A A
ARRM and CMPM flags are not set when APB clock is slower than kernel clock ARRM and CMPM flags are not set when APB clock is slower than kernel clock A A
Interrupt status flag is cleared by hardware upon writing its corresponding bit in LPTIM_DIER register Interrupt status flag is cleared by hardware upon writing its corresponding bit in LPTIM_DIER register N N
IWDG IWDG is stopped when BDRST is set IWDG is stopped when BDRST is set P P
RTC and TAMP Alarm flag may be repeatedly set when the core is stopped in debug Alarm flag may be repeatedly set when the core is stopped in debug N N
Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1 Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1 A A
Tamper flag set after tamper is disabled Tamper flag set after tamper is disabled N N
RTC calendar read may return transient incorrect value when BYPSHAD = 0 RTC calendar read may return transient incorrect value when BYPSHAD = 0 A A
Parasitic tamper detection when debugger is used in RDP Level 0 Parasitic tamper detection when debugger is used in RDP Level 0 A A
I2C Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period P P
Spurious bus error detection in controller mode Spurious bus error detection in controller mode A A
USART Data corruption due to noisy receive line Data corruption due to noisy receive line A A
Wrong data received by SPI slave receiver in autonomous mode with CPOL = 1 Wrong data received by SPI slave receiver in autonomous mode with CPOL = 1 A A
Received data may be corrupted upon clearing the ABREN bit Received data may be corrupted upon clearing the ABREN bit A A
Noise error flag set while ONEBIT is set Noise error flag set while ONEBIT is set N N
LPUART Possible LPUART transmitter issue when using low BRR[15:0] value Possible LPUART transmitter issue when using low BRR[15:0] value P P
SPI Possible corruption of last-received data depending on CRCSIZE setting Possible corruption of last-received data depending on CRCSIZE setting A A
MODF flag cannot generate interrupt MODF flag cannot generate interrupt A A
RDY output failure at high serial clock frequency RDY output failure at high serial clock frequency N N
Master communication suspension fails in autonomous mode Master communication suspension fails in autonomous mode N N
SPE may not be cleared upon MODF event SPE may not be cleared upon MODF event A A
SPI slave stalls with masters not providing extra SCK periods upon Not ready signaling SPI slave stalls with masters not providing extra SCK periods upon Not ready signaling A A
Truncation of SPI output signals after EOT event Truncation of SPI output signals after EOT event A A
TIFRE flag wrongly set in slave PCM long frame mode if FIXCH = 1 TIFRE flag wrongly set in slave PCM long frame mode if FIXCH = 1 N N
TIFRE flag never set in slave PCM/I2S mode if FIXCH = 0 TIFRE flag never set in slave PCM/I2S mode if FIXCH = 0 N N
FDCAN Desynchronization under specific condition with edge filtering enabled Desynchronization under specific condition with edge filtering enabled A A
Tx FIFO messages inverted under specific buffer usage and priority setting Tx FIFO messages inverted under specific buffer usage and priority setting A A
USB Buffer description table update completes after CTR interrupt triggers Buffer description table update completes after CTR interrupt triggers A A

The following table gives a quick reference to the documentation errata.

Table 4. Summary of device documentation errata
FunctionSectionDocumentation erratum
System VDDUSB is internally connected to VDD in WLCSP56 packages VDDUSB is internally connected to VDD in WLCSP56 packages
SRAM ECC error flags and addresses are updated only if interrupt is enabled SRAM ECC error flags and addresses are updated only if interrupt is enabled
ADC1 14-bit ADC offset error and integral linearity error values are increased in datasheets 14-bit ADC offset error and integral linearity error values are increased in datasheets
SAES Data transfer from TAMP_BKPxR to key registers must be done only in ascending order when KEYSEL[2:0] is set to 010 or 100 Data transfer from TAMP_BKPxR to key registers must be done only in ascending order when KEYSEL[2:0] is set to 010 or 100