For all STM32 MCUs, the number of bytes to be transferred at each pixel clock depends on the extended data mode:
- When the DCMI is configured to receive 8-bit data, the camera interface takes four pixel clock cycles to capture a 32-bit data word.
- When the DCMI is configured to receive 10-, 12-, or 14-bit data, the camera interface takes two pixel clock cycles to capture a 32-bit data word.
The table below summarizes the maximum data flow depending on the data width configuration.
In some applications, the DMA2 (or the DMA1 for the STM32H7 and STM32L4+; the GPDMA1 for the STM32U5 and STM32N647/657; and the GPDMA1 and GPDMA2 for the STM32H5) is configured to serve other requests in parallel with the DCMI request. In this case, the user must pay attention to the stream priority configurations, and consider the performance impact when the DMA serves other streams in parallel with the DCMI.
For better performance, when using the DCMI in parallel with other peripherals having requests that can be connected to either DMA1 or DMA2, or to GPDMA1 and GPDMA2, it is better to configure these streams to be served by the DMA/GPDMA that is not serving the DCMI.
The user must make sure that the DCMI supports the pixel clock configured on the camera module side to avoid the overrun.
It is recommended to use the highest system speed HCLK for better performance. However, the user must consider the speed of all the peripherals used (for example the speed of external memories) to avoid an overrun and to ensure the successful operation of the application.
The DCMI is not the only AHB peripheral but there are many other peripherals. The DMA is not the only master that can access the AHB peripherals. Using many AHB peripherals or other masters accessing the AHB peripherals leads to a concurrency on the AHB: the user must consider its impact on performance.
