GPDMA burst

An elementary programmed data transfer is a GPDMA burst (burst of data read from the source, or burst of data written to the destination), and is defined by:

A programmed data width: 8-, 16-, or 32-bit (via S/DDW_LOG2[1:0] in GPDMA_CxTR1)
A programmed burst length: 1 to 64 (via S/DBL_1[5:0] in GPDMA_CxTR1)

The burst size can be separately programmed for the source and the destination.

A burst is a series of n = 1 to 64 beats. Each beat is one data transfer, and has the same data width. For example, a 4-word burst is a burst of four 32-bit words. A burst with a burst length of 1 is named single.

The GPDMA issues a beat with the data width such as programmed: the programmed data width is never changed by the GPDMA implementation.

The GPDMA does not always issue a burst with the burst length as programmed on the allocated AHB master port. A GPDMA burst is implemented in hardware in one of the following ways:

With a same AHB transaction on the allocated master port
By a series of bursts of lower length or/and singles, due to any of the following conditions:
- Burst size higher than half of the FIFO size
- Block size (defined as the source block size) is not a multiple of the source data width.
- AHB constraints:
  - On a 1-Kbyte address boundary crossing
  - Burst that must be an incremental burst of 4, 8 or 16 beats

The GPDMA implementation guarantees the data integrity versus the programmed addressing, and maximizes the performance by implementing the largest allowed burst size compared to the programmed burst.

It is recommended to program a GPDMA burst of half of the FIFO size of the allocated GPDMA channel.

Table 4. Maximum achievable GPDMA burst length versus data width and channel number
Channel number	Data width access (bits)	Maximum burst length (beats)
STM32H503, STM32H523/533, STM32H562, STM32H563/573, STM32H543/553: 0 to 3 or 8 to 11 (8-byte FIFO) STM32H7Rx/7Sx, STM32N6, and STM32U5: 0 to 11 (8-byte FIFO) STM32U3 and STM32H5Ex/5Fx: 0 to 7 (8-byte FIFO)	8	Up to 4
	16	Up to 2
	32	1
STM32H503, STM32H523/533, STM32H562, STM32H563/573, STM32H543/553: 4 to 7 or 12 to 15 (32-byte FIFO) STM32H7Rx/7Sx, STM32N6 and STM32U5: 12 to 15 (32-byte FIFO) STM32U3 and STM32H5Ex/5Fx: 8 to 11 (32-byte FIFO)	8	Up to 16
	16	Up to 8
	32	Up to 4

A GPDMA burst is an elementary chunk of data that is at a fixed address or at a contiguously incremented address. For channels 6 to 7 and 14 to 15 for STM32H5, 10 to 11 for STM32U3 and STM32H5Ex/5Fx, and 12 to 15 for others (2D addressing capable), a first address jump may be performed after a burst. For getting a 2D buffer in memory, the user may have to program a burst, which is different from the typical 4-word burst. The GPDMA implementation automatically optimizes the performances, and includes this programmed constraint.

One GPDMA arbitration clock cycle is added before each programmed burst, provided that this burst size is lower than half of the FIFO size. Each data transfer can be a single data transfer, with a data arbitration performed each time a data has to be sent on the AHB bus master, or grouped into a burst data transfer to send few data back-to-back, without any possible GPDMA preemption after a GPDMA single arbitration phase. This minimizes the data transfer time (overall latency), and maximizes the throughput and the bus efficiency.

The main advantages of a transfer considering burst with more than one beat/data are the following:

The GPDMA arbitration is reduced to only one phase, which is applied for all the data defined by the burst size.
The burst is not interruptible at the GPDMA (arbitration) level, provided that its size is lower than half of the FIFO size. The latency for a set of number of read/written data is reduced and earlier completed (except for the very first beat).
If the targeted source or destination is an internal memory, the programmed addressed-incremented burst is implemented by incremented AHB bursts on the AHB bus. This consumes less bus cycles, and frees bus bandwidth for other possible concurrent masters, or enables the bus to be programmed at a lower bus frequency for a given traffic/bandwidth.
If the targeted source or destination is a peripheral register at a fixed address supporting a burst (with a FIFO mechanism like ADC1, OCTOSPI, or HASH), program a GPDMA 4-word fixed burst (which is after GPDMA arbitration split to four single transfers for being AHB compliant) increases the back-to-back transfer throughput since the arbitration clock cycle penalty occurs once.

Having a GPDMA burst with an AHB burst transaction increases the latency to serve other concurrent GPDMA transfers over the same allocated AHB master port, meanwhile it is performed. All other GPDMA requested transfers on the same GPDMA port are pending during this time (as well as all other masters intending to read or write data from/to the same target peripheral/memory). It is recommended to manage the different application requirements by programming channel priorities, as highlighted in GPDMA channel priority.

GDMA request

The GPDMA transfer can be initiated by setting a software request (via SWREQ in GPDMA_CxTR2), potentially associated to a hardware trigger defined by TRIGSEL[5:0] in the same register. This is the case for memory‑to‑memory transfers, which do not rely on any hardware request signal coming from the memory.

The hardware trigger may be driven by a peripheral (such as timers), by the GPDMA itself (channel transfer complete), or by other peripherals. Refer to the product reference manual for more details about the trigger functionalities, and more specifically in the GPDMA implementation section for the product-dependent list of triggers, which can be mapped to the GPDMA.

The memory-to-memory mode is also used for some timer configurations in DMA mode and for GPIOs configuration in DMA mode (see GPDMA configuration for communication, audio and mathematical peripherals and GPDMA configuration for cryptographic peripherals).

One GPDMA dead clock cycle is inserted between two back-to-back half data transfers (one dead cycle between two reads, one dead cycle between two writes) of a same channel in memory-to-memory mode.

As an alternative to a software request, a GPDMA transfer may be requested and initiated by an input hardware request coming from a peripheral, for peripheral-to-memory and memory-to-peripheral GPDMA transfers. The user must program SWREQ = 0 and REQSEL[6:0] in GPDMA_CxTR2 in order to select the proper hardware peripheral request among the product-dependent list of the mapped GPDMA request signals. Refer to the GPDMA implementation section of the product reference manual for this list and mapping.

Back-to-back data transfers to/from the peripheral are limited in performance by the fact that at least four AHB clock cycles must occur between two occurrences of a same peripheral request, due to the hardware protocol of the request/acknowledge between the peripheral and the GPDMA. This limitation does not happen for transfers to/from memory.

A hardware requested transfer can also be conditioned and associated to a hardware trigger, like for the memory‑to‑memory mode.

Peripherals, memories, and GPDMA configuration

Most of analog and digital peripherals in the STM32 devices with GPDMA have capabilities to handle data transfer without CPU intervention. They propose different possible configurations to fit with most of the application requirements.

The overall system performance results from the GPDMA configuration on each peripheral, depending on its location (bus type), its priority for the data transfer, and its capability to offer internal FIFOs for burst operation (the burst size is directly linked to the FIFO size of the peripheral, and the embedded FIFO connected to the associated GPDMA channel).

In the following sections, an exhaustive list of peripherals/memories embedded into the STM32 devices is presented to guide the developers for optimal GPDMA configuration, and to get the best benefit in term of performance.

For each peripheral, the following list of items is covered to help for peripheral and GPDMA configuration:

Peripheral request signals to GPDMA
- Most of peripherals requests are of single type or burst type.
- On the contrary, the lptimer_ue request (lptimer update event) requires a block-type GPDMA specific programming. BREQ must be set in GPDMA_CxTR2. This BREQ field is present in any channel.
- I3C receive data request to GPDMA (of single type) is specific: the number of data to be received during an I3C SDR private read message may be early completed by the external I3C device. In order to be supported by the GPDMA hardware, the field PFREQ must be set in DMA_CxTR2. It is to note that this field is present only on channels 0, 1, 8, and 9. This peripheral-flow control is different from any other peripheral DMA request (used in DMA‑flow control): the programmed DMA block size (BNDT[15:0] of DMA_CxBR1) is used for the block‑level transfer completion.
Peripheral bus (which AHB/APB)
Peripheral FIFO (unit cell, size)
Peripheral register access
- Most of the GPDMA requests are tightly coupled to one specific peripheral register.
- On the contrary, timers offer the flexibility to address different peripheral registers to fit different application requirements.
GPDMA read/write access
GPDMA port preference if any
GPDMA channel preference if any
GPDMA data width: 8-, 16-, or 32-bit
GPDMA burst length: 1 or 4

GPDMA configuration for internal memories

The STM32 devices embed a flash memory and multiple internal SRAMs. All these memories can be targeted as source or/and destination by the GPDMA to perform data transfer during respectively a requested memory-to-peripheral/peripheral-to-memory transfer.

A GPDMA programmed 32-bit data width is preferred to reduce the 32-bit AHB bus load on the allocated source/destination port to read from/write to the memory. This reduces the traffic to the memory by a ratio of four versus performing byte access, and by half versus handling half-words. This also reduces, in the same way by four or by half, the memory footprint, allowing a memory compacted with contiguous data. This configuration must be used as much as possible because the GPDMA, with its channel FIFO, can decorrelate the source data width versus the destination data width, and can perform FIFO queuing, data handling like packing and unpacking.

Using a different data width in source and destination provides constraints to the application:

Peripheral-to-memory mode: if 8-/16-bit reads are performed from the peripheral data register to the FIFO, meanwhile the FIFO performs byte-to-word packing and 32-bit writes are performed to the compacted memory, the application must guarantee that the read source block size is a multiple of 4 bytes (which may not be acceptable).
Memory-to-peripheral mode: if 32-bit reads are performed from the compacted memory to the FIFO, meanwhile the FIFO performs word-to-byte unpacking, and 8-bit writes are performed to the peripheral data register, the read source block size must be a multiple of 4 bytes.

If the application cannot guarantee that the buffer/block size is a multiple of 4 bytes or 2 half-words, then the user must program a lower data width than the 32-bit AHB bus, and the AHB bus load is not optimized. Another implementation alternative for the application is to split the block transfer into two LLI/block transfers, with one block multiple of 4 bytes for most of transfers, and another block with the residual byte(s).

For example, the I2C peripheral has a data register containing only 8-bit lsb data, and must be handled as a byte-stream on the peripheral side. The other transfer to/from the memory may take the benefit of the 32-bit AHB bus, performs 32-bit data width access, and a contiguously incremented memory address (provided that the allocated buffer/block size is a multiple of 4 bytes). This reduces by four the required bandwidth on the memory, and by four the memory footprint versus a byte-based addressing.

Another example is the ADC1 used in DMA mode with an 8-bit resolution mode:

The ADC must be configured 8-bit reads to the fixed peripheral data register address (with a right alignment, must have a 32-bit aligned address). The benefit is to be able to push only significant bytes into the GPDMA channel FIFO. As same channel has an 8-byte FIFO, the source burst can be programmed as a 4-byte burst (half size of the FIFO), which minimizes the GPDMA arbitration overhead.
The memory can be accessed with 32-bit words, GPDMA packing, and GPDMA write bursts with a 32-bit data width, and a contiguously incremented memory address (provided that the allocated buffer/block size is a multiple of 4 bytes). This reduces by four the required bandwidth on the memory, and by four the memory footprint versus a byte-based addressing.

For peripheral-to-memory or memory-to-peripheral GPDMA transfers, the GPDMA transfer is initiated when the hardware request (selected by REQSEL[6:0] in GPDMA_CxTR2) is asserted from the peripheral, and after that the GPDMA arbiter acknowledges the peripheral request. Refer to the product reference manual for more details.

All these memories can be used for memory-to-memory transfers, with a recommended 32-bit data width for source and destination. If a channel with 8‑word FIFO is allocated, memory transfers can benefit from being programmed and implemented as 4‑word bursts (half of the FIFO size), in order to get higher throughput and back-to-back data transfers.

For memory-to-memory transfers, channels with 2D addressing must be allocated if a 2D addressing mode is required.

The lowest priority (priority 0) is recommended for such a channel with memory-to-memory burst transfers in order to be used as best effort traffic, and preempted by the time-sensitive traffic (priority 3), but also other traffic to/from hardware peripherals (priority 1 and 2). See GPDMA channel allocation.

The memory-to-memory transfer does not rely on any hardware request directly from the memory. The GPDMA transfer is initiated by setting SWREQ in GPDMA_CxTR2, associated to potential triggers defined by TRIGSEL[5:0] in the same register. Refer to the product reference manual for more details.

The memory-to-memory mode can be triggered by a GPDMA trigger coming from a peripheral (such as timers), or thanks to some additional triggers sent by the GPDMA itself or coming from other peripherals. GPIOs are accessed in memory-to-memory mode.