GPDMA configuration for analog peripherals

Analog-to-digital converter ADC

The STM32 devices embed up to three analog-to-digital converters (ADC1, ADC2 and ADC3).

This analog-to-digital (A/D) converter implementation proposes a DMA mode. The GPDMA request signal is used by the hardware to request a new single converted sample to be read by the GPDMA whenever the peripheral needs it. The GPDMA reads the ADC_DR register. This ADC 16-bit or 32-bit data register must be accessed by a 32-bit word-aligned read access, with a programmed source data width being typically either 8-bit, 16-bit, or 32-bit and with a fixed addressing.

Table 5 ADC peripheral information summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the ADC is connected, and peripheral register from/to which the GPDMA must be programmed to read or write.

Table 5. ADC peripheral information
Peripheral request to GPDMA	Peripheral bus	Peripheral FIFO (unit, size)	Peripheral register access	Comments
adcx_dma (x = 1, 2, 3)	AHB1 for STM32N6 and AHB2 for others	None or 8-word FIFO depending on the STM32	Read ADC_DR	The ADC1/2/3 data register (ADC_DR) must be read with a 32-bit aligned address, whatever the data width.

The table below shows the supported and recommended GPDMA settings to be used for serving the ADC peripheral request: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length.

Table 6. GPDMA recommendation for ADC
GPDMA source port	GPDMA source burst		GPDMA channel	Comments
GPDMA source port	GPDMA data width	GPDMA burst length	GPDMA channel	Comments
Port 0^¹	8-, 16-, or 32-bit	1 or 4	Channel with 2‑word FIFO in single‑data mode and channel with 8‑word FIFO in burst mode	The default recommended setting balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear_addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For others STM32, For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO.

The ADC generates an analog watchdog trigger signal which can be used as trigger for any GPDMA transfer.

¹ By default, port 0 is recommended to access peripheral register, and port 1 to access memory if no specific requirements.

Analog-to-digital converter ADC4

This analog-to-digital (A/D) converter implementation only in STM32U5 proposes a DMA mode.

The GPDMA request signal is used by the hardware to request a new single converted sample to be read by the GPDMA whenever the peripheral needs it. The GPDMA reads the ADC_DR register.

This ADC 16-bit data register must be accessed by a 32-bit word-aligned read access, with a programmed source data width being typically either 8- or 16-bit, and with a fixed addressing.

The ADC4 implementation uses no FIFO for ADC_DR. No burst performance can be achieved for the read access to the ADC1. A channel 0 to 11 can be allocated.

The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the ADC4 is connected, and peripheral register from/to which the GPDMA must be programmed to read or write.

Table 7. ADC4 peripheral information
Peripheral request to GPDMA	Peripheral bus	Peripheral FIFO (unit, size)	Peripheral register access	Comments
adc4_dma	AHB3	None	Read ADC_DR	The ADC4 data register (ADC_DR) must be read with a 32-bit aligned address, whatever is the data width.

Table 8 GPDMA recommendation for ADC4 shows the supported and recommended GPDMA settings to be used for serving the ADC1/ADC12 peripheral request: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length.

Table 8. GPDMA recommendation for ADC4
GPDMA source port	GPDMA source burst		GPDMA channel	Comments
GPDMA source port	GPDMA data width	GPDMA burst length	GPDMA channel	Comments
Port 0^¹	8-, 16-, or 32-bit	1	0 to 11 typically	The default recommended setting balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel 0 to 11 to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations.

The ADC4 generates an analog watchdog trigger signal (adc4_awd1) which can be used as trigger for any GPDMA transfer.

¹ By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.

Digital-to-analog converter DAC

The STM32 devices have a digital-to-analog (D/A) converter DAC except for STM32H7Rx/7Sx and STM32N6.

The digital-to-analog converter DAC is DMA capable without embedded FIFO. Even if the DAC has a dual channel GPDMA capability (completely independent), it can also use a single GPDMA channel to transfer within a single GPDMA channel the data to the dual converter. The DAC proposes then a GPDMA optimization reducing the number of GPDMA channel to use from two to one. It also reduces the number of transactions on the AHB bus by packing the data of the two converters in a single data transfer (in dual mode).

Table 9. DAC peripheral information
Peripheral request to GPDMA	Peripheral bus	Peripheral FIFO (unit, size)	Peripheral register access	Comments
dac_ch1_dma/dac1_dma dac_ch2_dma/dac2_dma	AHB2	None	Write (any) DAC_DHRyRx with y = 12, 8 and x = 1, 2	The DAC data hold register must be written at the specific 32-bit aligned address, depending on the used DAC format (8- or 12‑bit, left-aligned or right-aligned) and depending on the considered channel (1 or 2).

The table below shows the supported and recommended GPDMA settings to be used for serving the DAC peripheral request: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).

Table 10. GPDMA recommendation for DAC
GPDMA destination port	GPDMA destination burst		GPDMA channel	Comments
GPDMA destination port	GPDMA data width	GPDMA burst length	GPDMA channel	Comments
Port 0^¹	8-, 16-, or 32-bit	1	Channels with 2‑word FIFO	The default recommended setting balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO.

¹ By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.

GPDMA configuration for graphic peripherals

DCMI (digital camera interface)

DCMI is available on STM32N6, STM32U5 and STM32H5 devices (excluding STM32H503 and STM32H543/553).

The DCMI is not burst capable when doing GPDMA transfers, even if an embedded FIFO is present. All transfers need to be handled in single data mode by the GPDMA controller since the DCMI sends a DMA request each time 32‑data are available.

The GPDMA reads the 32-bit DCMI_DR register. This 32-bit data register must be accessed with a programmed source data width being 32-bit and with a fixed addressing.

No burst performance can be achieved for the read access to the DCMI. Channels with 2-word FIFO can be allocated, unless channels with 8-word FIFO are free/unallocated and the required performances in terms of bandwidth are significant for this AHB peripheral. Channels with 8-word FIFO may be also allocated if the accessed memory is external.

The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the peripheral is connected, and peripheral register from/to which the GPDMA must be programmed to read.

Table 11. DCMI peripheral information
Peripheral request to GPDMA	Peripheral bus	Peripheral FIFO (unit, size)	Peripheral register access	Comments
dcmi_dma	AHB5 for STM32N6 and AHB2 for others	8‑word FIFO	Read 32-bit DCMI_DR	The DCMI can group two pixels within a single data transfer (data packing), depending on the image format sent by the camera sensor, for optimized utilization of the 32-bit AHB bus.

The table below shows the supported and recommended GPDMA settings to be used for serving the DCMI peripheral request: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).

Table 12. GPDMA recommendation for DCMI
GPDMA source port	GPDMA source burst		GPDMA channel	Comments
GPDMA source port	GPDMA data width	GPDMA burst length	GPDMA channel	Comments
Port 0^¹	32-bit	1	Channels with 2‑word FIFO Channels with 8-word FIFO especially if remains unallocated/free channels for such AHB peripherals which may require significant bandwidth	The default recommended setting balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear_addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performance, the channel allocation can be one of channels (with 8-word FIFO).

¹ By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.

JPEG codec

This section only applies to STM32U5Fx/5Gx, STM32N6 and STM32H5Ex/5Fx devices.

The hardware 8-bit JPEG codec encodes uncompressed image data streams or decodes JPEG-compressed image data streams. This peripheral has a DMA mode for streaming the input/output buffer from/to memory. The JPEG is burst capable, and includes a separated 16-word FIFO for input and output.

When the JPEG input FIFO is (at least) half empty (8-word free space), a new peripheral request jpeg_rx_dma is asserted: the DMA can write eight times the JPEG_DIR input data register.

When the JPEG output FIFO is half full (it contains an 8-word data), a new peripheral request jpeg_tx_dma is asserted: the DMA can read eight times the JPEG_DOR output data register.

An 8-word fixed burst must be programmed on the DMA side to write/read the JPEG input/output data register, whatever the DMA channel allocation. GPDMA transfers are then implemented by a series of either single words or 2-word, 3-word, or 4-word DMA bursts. For improved burst performances (with lower GPDMA arbitration cycles), one GPDMA channel 8-word FIFO must be allocated.

For JPEG encoding, the output JPEG-compressed stream must be managed with peripheral-flow control. The allocated DMA channel x must be programmed with DMA_CxTR2.PFREQ = 1.

Table 13. JPEG peripheral information
Peripheral request to GPDMA	Peripheral bus	Peripheral FIFO (unit, size)	Peripheral register access	Comments
jpeg_rx_dma	AHB5 for STM32N6 and AHB1 for others	16-word input FIFO	Write 32-bit JPEG_DIR	Request for 8 words as soon and as long as the input FIFO level is half empty (8-word space)
jpeg_tx_dma	AHB5 for STM32N6 and AHB1 for others	16-word output FIFO	Read 32-bit JPEG_DOR	Request for 8 words as soon and as long as the input FIFO level is half full (8-word)

The table below shows the supported GPDMA settings to be used for serving the JPEG peripheral request in terms of data width and burst length.

Table 14. GPDMA recommendation for JPEG
GPDMA source/destination port	GPDMA source/destination burst		Comments
GPDMA source/destination port	GPDMA data width	GPDMA burst length	Comments
Port 0^¹	32-bit	8	The default recommended setting balances bandwidth over each port (port 0 for peripheral, port 1 for the memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. During JPEG encode, the allocated DMA channel x for the output compressed stream must be programmed with the peripheral flow control (DMA_CxTR2.PFREQ = 1). An 8-word burst must be DMA programmed for any channel. The DMA can issue a single word or a 2-, 3-, or 4-word burst (or an 8-word only for channels with 8-word FIFO). For improved burst performance (lower GPDMA arbitration), one of the GPDMA channels with 8-word FIFO can be allocated.

¹ By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.